476
P. Vianco and M. Neilsen
is also the PCB—laminate or ceramic—to which is attached the component. The
introduction of encapsulants, underfills, and conformal coatings further complicate
the overall stacked package structure. The variety of materials sets and geometries
present by PoP and PoPoP components limits the practicality of empirical programs
to obtain accelerated aging data for predicting the TMF of the solder joints. Computational modeling, together with validation tests of more limited scope, are finding
greater use in predicting the reliability of stacked package solder joints as required
for high-reliability applications.
16.2 Soldering Assembly Processes
A contributing factor to yield loss within stacked package technology are solder
joint defects, which are caused by warpage [3, 4]. The study described in Ref.
[4] examined, specifically, the role of the top package’s material properties—CTE,
modulus, etc.—on the extent of its warpage during the reflow process. Unfortunately, the process engineer rarely has control over the material properties of PoP or
PoPoP packages in order to minimize defects during the assembly process. Therefore, the topic of warpage is highlighted in the Soldering Assembly Process section
because its effect is felt most strongly at assembly. As such, optimizing the assembly
process parameters during product development provides the best avenue to minimize
warpage behavior.
The following sections provide overviews of important factors within the soldering
assembly process; they include solder alloys, fluxes and pastes, assembly methodologies, conformal coatings and underfills, as well as inspection techniques as they
pertain to stacked packaging technology. Also, as noted above, the discussion will
address warpage.
16.2.1 Solder Alloys
16.2.1.1 Sn–Pb Solders
The advent of stacked packages, whether early versions that combined peripherally leaded packages or the current area-array geometries, used the eutectic Sn–
Pb solder. This alloy has the composition of 63Sn–37Pb (wt%) and equivalent
solidus and liquidus temperatures of T solidus (T s ) and T liquidus (T l ) = 183 °C. The
soldering processes are well established in the electronics community and use relatively low reflow process temperatures in the range of 220–235 °C. Lower process
temperatures are always the prudent path to minimize warpage-related defects. Most
high-reliability electronics are still assembled with Sn-Pb solder.
P. Vianco and M. Neilsen
is also the PCB—laminate or ceramic—to which is attached the component. The
introduction of encapsulants, underfills, and conformal coatings further complicate
the overall stacked package structure. The variety of materials sets and geometries
present by PoP and PoPoP components limits the practicality of empirical programs
to obtain accelerated aging data for predicting the TMF of the solder joints. Computational modeling, together with validation tests of more limited scope, are finding
greater use in predicting the reliability of stacked package solder joints as required
for high-reliability applications.
16.2 Soldering Assembly Processes
A contributing factor to yield loss within stacked package technology are solder
joint defects, which are caused by warpage [3, 4]. The study described in Ref.
[4] examined, specifically, the role of the top package’s material properties—CTE,
modulus, etc.—on the extent of its warpage during the reflow process. Unfortunately, the process engineer rarely has control over the material properties of PoP or
PoPoP packages in order to minimize defects during the assembly process. Therefore, the topic of warpage is highlighted in the Soldering Assembly Process section
because its effect is felt most strongly at assembly. As such, optimizing the assembly
process parameters during product development provides the best avenue to minimize
warpage behavior.
The following sections provide overviews of important factors within the soldering
assembly process; they include solder alloys, fluxes and pastes, assembly methodologies, conformal coatings and underfills, as well as inspection techniques as they
pertain to stacked packaging technology. Also, as noted above, the discussion will
address warpage.
16.2.1 Solder Alloys
16.2.1.1 Sn–Pb Solders
The advent of stacked packages, whether early versions that combined peripherally leaded packages or the current area-array geometries, used the eutectic Sn–
Pb solder. This alloy has the composition of 63Sn–37Pb (wt%) and equivalent
solidus and liquidus temperatures of T solidus (T s ) and T liquidus (T l ) = 183 °C. The
soldering processes are well established in the electronics community and use relatively low reflow process temperatures in the range of 220–235 °C. Lower process
temperatures are always the prudent path to minimize warpage-related defects. Most
high-reliability electronics are still assembled with Sn-Pb solder.