13 Fundamentals of Heat Dissipation in 3D IC Packaging …
383
We adopt wormhole switching for wireline links in the 3D wireless NoC where
data packets are broken down into flow control units or flits [26]. In the wireless interconnections, the wormhole switching is modified as discussed in the next subsection
to enable wireless communication. Instead of using XYZ routing typically used in
3D NoCs, in the 3D-HiWiNoC architecture, shortest path routing is adopted to take
advantages of the long-range wireless communications. We use a forwarding-table
based routing over pre-computed shortest paths determined by Dijkstra’s algorithm.
Dijkstra’s algorithm extracts a minimum spanning tree, which provides the shortest
path between any pair of nodes in a graph.
13.6.4.4 Performance of the 3D WiNoC
In this section, we evaluate the performance of the token-based 3-D hierarchical
WiNoC (3D-THiWiNoC) architecture for system size of 64 cores with uniform
random traffic pattern in terms of energy cost per bit and peak network bandwidth and
compare it with 3D wireline mesh architecture for two different flit sizes of 32 bits
and 256 bits respectively. Energy cost per bit is the energy dissipated in transferring
one bit completely from source to destination at network saturation. Peak bandwidth
is the maximum achievable data rate for the NoC. The bandwidth is measured as the
average number of bits successfully arriving per core per second. Specifically, we
consider the following configurations:
1. 3D Mesh NoC with TSV with conventional air-cooled heat sink (3D-MTSV)
adopted from [39]. For this architecture, each switch is connected to its cardinal
neighbors as well as its vertical neighbors above and below itself. Dimensionorder XYZ routing is adopted for this architecture.
2. Token-based 3D hierarchical wireless NoC with interlayer cooling (3DTHiWiNoC) as proposed here.
The power dissipations of the cores, the NoC switches, and interconnects as well
as the impacts of the cooling infrastructures and wireless transceivers are considered
for evaluation of the temperatures. The maximum chip temperature can be either the
temperature of a core, link or switch. It is important to note that we did not incorporate
any dynamic thermal management technique for this experiment as our goal was to
study the effectiveness of two cooling approaches (conventional forced air-cooling
and inter-layer liquid cooling) considered in this subsection. Table 13.1 shows the
maximum chip temperature for each of the architectures studied here for two different
flit sizes. For interlayer coolers, we used a thermal resistance of 0.4 K/W as noted in
Sect. 4.1. From the table, it can be seen that for flit size of 32 bits, maximum steady
state temperature of the 3D-MTSV reaches 102.17 °C with forced-air cooling based
conventional heat sink. Whereas with interlayer layer cooling, it decreases by 35.5%
for 3D-HiWiNoC architecture.
We also consider an architecture with 3D-MTSV architecture with liquid cooling
layers (3D-MTSV-Cooling). In this architecture the TSV based vertical links are only
preserved in alternate rows of switches. This is because the microchannels are routed
383
We adopt wormhole switching for wireline links in the 3D wireless NoC where
data packets are broken down into flow control units or flits [26]. In the wireless interconnections, the wormhole switching is modified as discussed in the next subsection
to enable wireless communication. Instead of using XYZ routing typically used in
3D NoCs, in the 3D-HiWiNoC architecture, shortest path routing is adopted to take
advantages of the long-range wireless communications. We use a forwarding-table
based routing over pre-computed shortest paths determined by Dijkstra’s algorithm.
Dijkstra’s algorithm extracts a minimum spanning tree, which provides the shortest
path between any pair of nodes in a graph.
13.6.4.4 Performance of the 3D WiNoC
In this section, we evaluate the performance of the token-based 3-D hierarchical
WiNoC (3D-THiWiNoC) architecture for system size of 64 cores with uniform
random traffic pattern in terms of energy cost per bit and peak network bandwidth and
compare it with 3D wireline mesh architecture for two different flit sizes of 32 bits
and 256 bits respectively. Energy cost per bit is the energy dissipated in transferring
one bit completely from source to destination at network saturation. Peak bandwidth
is the maximum achievable data rate for the NoC. The bandwidth is measured as the
average number of bits successfully arriving per core per second. Specifically, we
consider the following configurations:
1. 3D Mesh NoC with TSV with conventional air-cooled heat sink (3D-MTSV)
adopted from [39]. For this architecture, each switch is connected to its cardinal
neighbors as well as its vertical neighbors above and below itself. Dimensionorder XYZ routing is adopted for this architecture.
2. Token-based 3D hierarchical wireless NoC with interlayer cooling (3DTHiWiNoC) as proposed here.
The power dissipations of the cores, the NoC switches, and interconnects as well
as the impacts of the cooling infrastructures and wireless transceivers are considered
for evaluation of the temperatures. The maximum chip temperature can be either the
temperature of a core, link or switch. It is important to note that we did not incorporate
any dynamic thermal management technique for this experiment as our goal was to
study the effectiveness of two cooling approaches (conventional forced air-cooling
and inter-layer liquid cooling) considered in this subsection. Table 13.1 shows the
maximum chip temperature for each of the architectures studied here for two different
flit sizes. For interlayer coolers, we used a thermal resistance of 0.4 K/W as noted in
Sect. 4.1. From the table, it can be seen that for flit size of 32 bits, maximum steady
state temperature of the 3D-MTSV reaches 102.17 °C with forced-air cooling based
conventional heat sink. Whereas with interlayer layer cooling, it decreases by 35.5%
for 3D-HiWiNoC architecture.
We also consider an architecture with 3D-MTSV architecture with liquid cooling
layers (3D-MTSV-Cooling). In this architecture the TSV based vertical links are only
preserved in alternate rows of switches. This is because the microchannels are routed