Spin Transfer Torque Magnetoresistive Random Access Memory
69
intermediate layer is introduced to eliminate the stray field, but this increases the
stack complexity.
Furthermore, the required magnetic properties and thermal robustness of hard
layer limits the choice of materials to Co/X multilayers, where X is typically Pd, Pt
or Ni that can provide high PMA through magnetocrystalline anisotropy. In addition
to having low spin polarizing efficiencies required to create a spin current for STT
switching, such hard layers with fcc(111) crystallinity would not be able induce
bcc-MgO(100) growth required for high TMR. An additional ferromagnetic layer
(referred to as polarizing layer) with high spin polarizing efficiency can circumvent
the problem, but must be coupled to the SAF structure through amorphous texturebreaking layer, therefore adding complexity to the MTJ design.
Given the complexity involved, this chapter is devoted to the functions of each
section within the full pMTJ stack design as shown in Fig. 10b. Each subsection
will describe the rationale, compromises and limitations behind the current material
choices, as well as future outlook and development plans. The discussion is focused
on bottom-pinned pMTJ stack, wherein the stack begins with the reference section
as the first set of ferromagnetic layers to be deposited.
5.1 Seed Layer
One of the major challenges with the fabrication of MRAM stacks is the tight control
on the deposition process as the interfacial effects, crystallinity and surface roughness are critical to the performance of such complex multilayer structures. It is of
paramount importance to have an initial ultra-smooth seed layer to provide the crystalline template for the reference layer. Since Co/Pt multilayers are one of the de
facto choice as hard magnetic layers due to its high M s , high H c , high T c and high
tunability, the seed layer chosen should be in the fcc phase with minimal lattice
mismatch.
The seed layer candidates for Co/Pt multilayers are usually Ru and Pt, as they
have been demonstrated to promote the necessary crystallographic texture that retains
PMA even after 400 °C for at least 30 min [119, 120, 121]. While Ta has also been
reported before as a seed layer for Co/Pt multilayers [122, 123], it is also well known
to lack the thermal robustness required for pMTJ to be compatible with CMOS BEOL
processes [122, 123, 124, 125, 126]. A thick Pt seed layer is desirable to achieve
high PMA in Co/Pt multilayers, but is typically reduced for practicality in pMTJ
fabrication [127, 128]. Pt, being an unreactive noble metal, can pose a challenge
when reactive ion etching is used in device patterning for fast throughput [120, 129,
130]. On the other hand, the redeposition as a result of Ru etching remains conductive
even after post-etch surface treatment via oxidation. Although Co/Pt multilayers
with high PMA has been achieved with 7 nm Ru seed layer, the risk of device
failure due to sidewall redeposition shorting the MTJ pillar increases as devices scale
down [120]. Other key considerations for seed layer include electrical conductivity,
400 °C thermal robustness and minimal thickness to allow larger process margin
69
intermediate layer is introduced to eliminate the stray field, but this increases the
stack complexity.
Furthermore, the required magnetic properties and thermal robustness of hard
layer limits the choice of materials to Co/X multilayers, where X is typically Pd, Pt
or Ni that can provide high PMA through magnetocrystalline anisotropy. In addition
to having low spin polarizing efficiencies required to create a spin current for STT
switching, such hard layers with fcc(111) crystallinity would not be able induce
bcc-MgO(100) growth required for high TMR. An additional ferromagnetic layer
(referred to as polarizing layer) with high spin polarizing efficiency can circumvent
the problem, but must be coupled to the SAF structure through amorphous texturebreaking layer, therefore adding complexity to the MTJ design.
Given the complexity involved, this chapter is devoted to the functions of each
section within the full pMTJ stack design as shown in Fig. 10b. Each subsection
will describe the rationale, compromises and limitations behind the current material
choices, as well as future outlook and development plans. The discussion is focused
on bottom-pinned pMTJ stack, wherein the stack begins with the reference section
as the first set of ferromagnetic layers to be deposited.
5.1 Seed Layer
One of the major challenges with the fabrication of MRAM stacks is the tight control
on the deposition process as the interfacial effects, crystallinity and surface roughness are critical to the performance of such complex multilayer structures. It is of
paramount importance to have an initial ultra-smooth seed layer to provide the crystalline template for the reference layer. Since Co/Pt multilayers are one of the de
facto choice as hard magnetic layers due to its high M s , high H c , high T c and high
tunability, the seed layer chosen should be in the fcc phase with minimal lattice
mismatch.
The seed layer candidates for Co/Pt multilayers are usually Ru and Pt, as they
have been demonstrated to promote the necessary crystallographic texture that retains
PMA even after 400 °C for at least 30 min [119, 120, 121]. While Ta has also been
reported before as a seed layer for Co/Pt multilayers [122, 123], it is also well known
to lack the thermal robustness required for pMTJ to be compatible with CMOS BEOL
processes [122, 123, 124, 125, 126]. A thick Pt seed layer is desirable to achieve
high PMA in Co/Pt multilayers, but is typically reduced for practicality in pMTJ
fabrication [127, 128]. Pt, being an unreactive noble metal, can pose a challenge
when reactive ion etching is used in device patterning for fast throughput [120, 129,
130]. On the other hand, the redeposition as a result of Ru etching remains conductive
even after post-etch surface treatment via oxidation. Although Co/Pt multilayers
with high PMA has been achieved with 7 nm Ru seed layer, the risk of device
failure due to sidewall redeposition shorting the MTJ pillar increases as devices scale
down [120]. Other key considerations for seed layer include electrical conductivity,
400 °C thermal robustness and minimal thickness to allow larger process margin