RRAM-Based Neuromorphic Computing Systems
399
device successfully demonstrated the key synaptic behaviors such as STP, LTP, and
spike-rate-dependent plasticity (SRDP).
NN Algorithms and Architectures
In order to reach the goal of having compact system that can facilitate robust large
scale NN, co-optimization from all aspects of the NN, i.e., device, circuit, and algorithm, must be thoroughly considered. With the device desired characteristics and
drawbacks discussed in the previous sections, suitable algorithms and architectures
must be implemented to efficiently utilize the specific device-circuit system.
As mentioned in [66], there are two ways of looking at RRAM based neuromorphic
algorithms. From the deep learning perspective, one is to design algorithms for
inference only, i.e., to map the pre-trained deep learning models which fulfil certain
hardware constraints onto the RRAM based neuromorphic hardware without any
further training. While another way is to perform on-chip training on the RRAM based
neuromorphic hardware, which will require additional interface circuitry, that is
usually unique to the algorithm implemented. Inference alone requires the conversion
of existing pre-trained deep learning algorithms in high precision digital domain
to the binary event-based (or spiking) domain to allow the mapping onto RRAM
based neuromorphic hardware. Whereas, on-chip training can be implemented at
the RRAM synapse in the neuromorphic hardware by emulating local spike timingbased algorithms such as spike timing dependent plasticity or its variants. These two
methods belong to a computational paradigm known as spiking deep neural network
(SDNN).
Other than the aforementioned learning algorithms that can be implemented on
RRAM based neuromorphic hardware, low precision convolutional neural networks
(CNN), such as the binarized neural network [67], binaryNet [68], XNOR-NET[69],
and DoReFa-NET [70], can be mapped onto a chip containing RRAM based synaptic
crossbar array [71]. In such approach, the computations performed in the CNN can
be converted to bitwise operations, such as bitwise convolution, batch normalization
and pooling etc. [71]. Contrary to other paradigms, mapping process is relatively
simpler with such approach as it does not involve spiking neurons. Irrespective of
the mapping algorithms implemented on the RRAM based neuromorphic hardware,
one should expect a drop-in accuracy due to hardware noise, especially the noise
inherent in RRAM synapses (Set or reset variability [72], Random Telegraph Noise
(RTN) [73], etc.). One plausible approach to mitigate the drop in accuracy is to
account for the noise itself during training, which may help to alleviate the accuracy
loss to some extent.
4 Computation in a Crossbar Array of RRAM Synapses
and Experimental Demonstration
The convolution operation in a CNN can be performed by using the crossbar array
of synapses in a neuromorphic core. For an example, a 3 × 3 convolution kernel is
399
device successfully demonstrated the key synaptic behaviors such as STP, LTP, and
spike-rate-dependent plasticity (SRDP).
NN Algorithms and Architectures
In order to reach the goal of having compact system that can facilitate robust large
scale NN, co-optimization from all aspects of the NN, i.e., device, circuit, and algorithm, must be thoroughly considered. With the device desired characteristics and
drawbacks discussed in the previous sections, suitable algorithms and architectures
must be implemented to efficiently utilize the specific device-circuit system.
As mentioned in [66], there are two ways of looking at RRAM based neuromorphic
algorithms. From the deep learning perspective, one is to design algorithms for
inference only, i.e., to map the pre-trained deep learning models which fulfil certain
hardware constraints onto the RRAM based neuromorphic hardware without any
further training. While another way is to perform on-chip training on the RRAM based
neuromorphic hardware, which will require additional interface circuitry, that is
usually unique to the algorithm implemented. Inference alone requires the conversion
of existing pre-trained deep learning algorithms in high precision digital domain
to the binary event-based (or spiking) domain to allow the mapping onto RRAM
based neuromorphic hardware. Whereas, on-chip training can be implemented at
the RRAM synapse in the neuromorphic hardware by emulating local spike timingbased algorithms such as spike timing dependent plasticity or its variants. These two
methods belong to a computational paradigm known as spiking deep neural network
(SDNN).
Other than the aforementioned learning algorithms that can be implemented on
RRAM based neuromorphic hardware, low precision convolutional neural networks
(CNN), such as the binarized neural network [67], binaryNet [68], XNOR-NET[69],
and DoReFa-NET [70], can be mapped onto a chip containing RRAM based synaptic
crossbar array [71]. In such approach, the computations performed in the CNN can
be converted to bitwise operations, such as bitwise convolution, batch normalization
and pooling etc. [71]. Contrary to other paradigms, mapping process is relatively
simpler with such approach as it does not involve spiking neurons. Irrespective of
the mapping algorithms implemented on the RRAM based neuromorphic hardware,
one should expect a drop-in accuracy due to hardware noise, especially the noise
inherent in RRAM synapses (Set or reset variability [72], Random Telegraph Noise
(RTN) [73], etc.). One plausible approach to mitigate the drop in accuracy is to
account for the noise itself during training, which may help to alleviate the accuracy
loss to some extent.
4 Computation in a Crossbar Array of RRAM Synapses
and Experimental Demonstration
The convolution operation in a CNN can be performed by using the crossbar array
of synapses in a neuromorphic core. For an example, a 3 × 3 convolution kernel is