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spin momentum which enables magnetization switching [2–6]. STT effect was
first proposed in theory in 1996 independently by Slonczewski and Berger [2, 6].
Eventually, practical STT switching was demonstrated, first in MTJ with AlO x
devices in 2004 then on MgO-based MTJ in 2005 [7–9]. These were MTJs with
in-plane magnetization that supports scaling but required a large writing current.
In 2010, the successful demonstration of perpendicular MTJ based on CoFeB-MgO
heterostructures allowed reduction in current switching accelerating industry demand
for STT-MRAM [10–14].
STT-MRAM belongs to a unique group of emerging non-volatile memories
(NVMs), which can eliminate standby power, a major bottleneck against scaling in
existing semiconductor memory solutions. Compared to other non-magnetic NVMs,
STT-MRAM is superior in terms of lower power consumption and faster writing
speed. However, compared to existing semiconductor solutions writing energy is
large—still in the sub-pJ/bit level at best [15–18]. This dynamic power consumption
predominantly comes from ohmic dissipation and is dependent on the large current
required for switching [19]. For applications in cache-memory or memory-intensive
computing, frequent rewriting is required for which STT is still not the best solution. An alternative solution for ultra-low power writing within the MRAM family
is through electric-field (or voltage) controlled magnetic anisotropy [19–35]. In this
scheme, the ohmic loss is significantly reduced since the current flowing through the
MTJ is significantly smaller. This approach has gained much momentum in recent
years because of the demonstration of write energies at two orders of magnitude
lower than the traditional STT approach [19, 36].
The potential benefits for E-field MRAM cannot be understated. Firstly, compared
to STT-MRAM, which requires an electrical current, an ideal MRAM based on the
electric-field would only consume the amount of energy need to charge and discharge
the MgO insulator. MTJ scalability and thicker MgO can both be implemented in this
scheme. The resulting small capacitance implies sub fJ/bit level charging energies
[23], putting it on a level with conventional CMOS SRAM or DRAM (1–10 fJ/bit)
[37]. Secondly, existing current consumption for STT-MRAM is directly proportional
to the area of the MTJ. This implies that variation in the programming current is
a squared function of the linear variation in the critical-dimension (CD). E-field
MRAM would eliminate this issue and reduce process-induced variations back to
a single dimension (the thickness of the MgO). Thirdly, conventional STT-MRAM
scaling is limited by the selected transistor strength. Typically the transistor pitches
are much larger than the MTJ in order to supply the amount of current needed for STTMRAM to operate. E-field MRAM could allow for more aggressive scaling, opening
up more avenues for MRAM to be used in applications that require extremely low
power consumption. As shown in Fig. 1a Electric Field-MRAM (EF-MRAM) can
provide superior performance both in writing energy and writing time. It is also
particularly suitable for cache memory (L1, L2) applications where writing speeds
faster than 10 ns are required (Fig. 1b).
In the following sections, we will discuss in detail, electric-field writing mechanism describing the physics, material dependence and their close relationship with
device operation.
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