Concretization and Morphware Networks 219
obtain such an arrangement on a single chip with rDPAs
(reconfigurable Datapath Arrays) and FPGAs.
Matrix architectures combining rDPA and FPGA must be
optimized so that the path taken between the different elements is as
short as possible. If the architecture is not appropriate, we
immediately see a significant loss of efficiency, but this is not
necessarily a major problem, if the overall circuit serves numerous,
very different algorithms. In fact, the best scenario is to know, in
advance, which algorithms will be executed on the circuit, with a view
to being able to optimize the logic elements, the memory and the path
that is followed. FPGAs are generally too fine-grained to be highly
efficient in terms of performance, and they need to be substituted with
coarser-grained elements that are better suited to the purposes of the
reconfigurable microprocessor.
Reconfiguration can take place when the circuit is engaged,
between two phases of execution, or even during the execution
of a process. Circuits which work at the bit level, such as FPGAs,
require a lot of time for reconfiguration, which is carried out by way
of a bitstream that is fairly complex in relation to coarse-grained
architectures, which require a much shorter binary stream, with much
quicker establishment. In fact, most reprogrammable cards have
partial reconfigurations that facilitate the execution of a function
whilst another part of the microprocessor continues to execute a
function.
Reconfigurable element matrices seem to represent the best
compromise between fine- and coarse-grained architectures, bringing
together enough circuits to find optimal chain paths. To control
this collection of circuits, a host processor is needed. The host needs
to be powerful to determine which algorithms to use to compute
the chain. Overall, the flexibility of the architecture hinges on
the path taken to interconnect the gates. Thus, the path to be
determined is of prime importance in carrying out complex functions,
such as those found in certain protocol- or signal processing
operations.
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obtain such an arrangement on a single chip with rDPAs
(reconfigurable Datapath Arrays) and FPGAs.
Matrix architectures combining rDPA and FPGA must be
optimized so that the path taken between the different elements is as
short as possible. If the architecture is not appropriate, we
immediately see a significant loss of efficiency, but this is not
necessarily a major problem, if the overall circuit serves numerous,
very different algorithms. In fact, the best scenario is to know, in
advance, which algorithms will be executed on the circuit, with a view
to being able to optimize the logic elements, the memory and the path
that is followed. FPGAs are generally too fine-grained to be highly
efficient in terms of performance, and they need to be substituted with
coarser-grained elements that are better suited to the purposes of the
reconfigurable microprocessor.
Reconfiguration can take place when the circuit is engaged,
between two phases of execution, or even during the execution
of a process. Circuits which work at the bit level, such as FPGAs,
require a lot of time for reconfiguration, which is carried out by way
of a bitstream that is fairly complex in relation to coarse-grained
architectures, which require a much shorter binary stream, with much
quicker establishment. In fact, most reprogrammable cards have
partial reconfigurations that facilitate the execution of a function
whilst another part of the microprocessor continues to execute a
function.
Reconfigurable element matrices seem to represent the best
compromise between fine- and coarse-grained architectures, bringing
together enough circuits to find optimal chain paths. To control
this collection of circuits, a host processor is needed. The host needs
to be powerful to determine which algorithms to use to compute
the chain. Overall, the flexibility of the architecture hinges on
the path taken to interconnect the gates. Thus, the path to be
determined is of prime importance in carrying out complex functions,
such as those found in certain protocol- or signal processing
operations.
www.it-ebooks.info