3. Oscilloscope: 9384 L, Teledyne LeCroy, USA.
4. Inverted microscope: Eclipse Ti-U, Nikon, Japan.
5. Charge-coupled device (CCD) Camera: Neo-sCMOS, Andor,
Northern Ireland.
3 Method
The fabrication and assembly of the microfluidic platform are performed in the clean room. Briefly, the microfluidic channel of the
bottom layer is fabricated by micromolding of PDMS. A silicon
model is first fabricated by deep reactive ion etching (DRIE). The
top layer consists of no patterns; thus it can be directly cured from
PDMS. The PC membrane is bonded between the two PDMS
layers with PDMS gel. The following methods are from an existing
protocol [9].
3.1 Microchannel
Fabrication by
Micromolding
1. Contact lithography is used to transfer photomask patterns
onto the photoresist layer of a silicon wafer.
2. The silicon wafer is spin coated with a uniform layer of 1.2 μmthick photoresist and exposed to UV light in the mask and
bond aligner before being placed in the developer.
3. The patterned photoresist is used as a mask for DRIE to
produce 10 μm tall silicon micropost arrays.
4. The silicon mold is cleaned with oxygen plasma and coated
with the FOTS solution at 65
C for 5 min to remove redundant surfactant.
5. The silicon mold is cleaned with pure heptane at 100
C for
10 min to strengthen the release layer.
3.2 Device Assembly
1. The bottom layer has a microchannel through which solution
with target molecules is introduced. The height of the microchannel is about 50 μm. To make the bottom layer, PDMS
solution with a ratio of 15:1 between base and curing agent is
poured onto the mold fabricated in the previous step. In order
to minimize the distance from microchannel to cells, the bottom layer needs to be very thin, typically 2–3 mm. Bake at
120
C for 30 min.
2. The top layer is a piece of PDMS without any patterns. Therefore, the same PDMS solution is poured onto a clean silicon
wafer. The top layer needs to be thick enough to hold cell
culture solution (~6 mm). Bake at 120
C for 30 min.
3. Gently peel off the PDMS layers from silicon wafers prepared in
steps 1 and 2. Stack two layers together, but make sure the side
without microchannel patterns faces the top layer.
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