262
Strain-Engineered MOSFETs
systematically set up to study the control over process parameters and arbitrary choice of device performance characteristics. The models developed
from DoE are known as process compact models (PCMs), which are analogous to compact models for semiconductor devices and circuits. PCMs may
be used to capture the nonlinear behaviour and multiparameter interactions
of manufacturing processes [7, 8]. SPICE process compact models (SPCMs)
can be considered an extension of PCMs applied to SPICE parameters. By
combining calibrated TCAD simulations with global SPICE extraction
strategy, it is possible to create self-consistent process-dependent compact
SPICE models, with process parameter variations as explicit variables. This
methodology brings manufacturing to design, so that measurable process
variations can be fed into design [9]. To design robust circuits using strainengineered MOSFETs, the effect of process variability on the circuit model
parameters is examined.
The process compact model methodology consists of TCAD simulations,
using the process and device models that are calibrated to strained Si and
process-dependent compact SPICE model extraction (Figure 9.12). The
parameter extraction is performed using the parameter extraction tool
Paramos [10], which interfaces TCAD or experimental data and directly
generates process-aware SPICE models. The process-aware SPICE models allow designers to account for process variability and develop more
robust designs.
The process compact model generation strategy includes the following:
(1) Capture the process-device relationships between the process parameters and device performance of a semiconductor manufacturing process.
(2) PCM is robust, fast to evaluate, and can be embedded into other environments such as PCM Studio, spreadsheet applications, and yield management
Manufacturing
TCAD
(Process & Device)
I/C-V Database {P i }
SPICE Extraction
Process-Aware Compact
SPICE model {P i }
Circuit Simulation
Calibration
{P i }
FIGURE 9.12
Compact SPICE model extraction and validation methodology.
Strain-Engineered MOSFETs
systematically set up to study the control over process parameters and arbitrary choice of device performance characteristics. The models developed
from DoE are known as process compact models (PCMs), which are analogous to compact models for semiconductor devices and circuits. PCMs may
be used to capture the nonlinear behaviour and multiparameter interactions
of manufacturing processes [7, 8]. SPICE process compact models (SPCMs)
can be considered an extension of PCMs applied to SPICE parameters. By
combining calibrated TCAD simulations with global SPICE extraction
strategy, it is possible to create self-consistent process-dependent compact
SPICE models, with process parameter variations as explicit variables. This
methodology brings manufacturing to design, so that measurable process
variations can be fed into design [9]. To design robust circuits using strainengineered MOSFETs, the effect of process variability on the circuit model
parameters is examined.
The process compact model methodology consists of TCAD simulations,
using the process and device models that are calibrated to strained Si and
process-dependent compact SPICE model extraction (Figure 9.12). The
parameter extraction is performed using the parameter extraction tool
Paramos [10], which interfaces TCAD or experimental data and directly
generates process-aware SPICE models. The process-aware SPICE models allow designers to account for process variability and develop more
robust designs.
The process compact model generation strategy includes the following:
(1) Capture the process-device relationships between the process parameters and device performance of a semiconductor manufacturing process.
(2) PCM is robust, fast to evaluate, and can be embedded into other environments such as PCM Studio, spreadsheet applications, and yield management
Manufacturing
TCAD
(Process & Device)
I/C-V Database {P i }
SPICE Extraction
Process-Aware Compact
SPICE model {P i }
Circuit Simulation
Calibration
{P i }
FIGURE 9.12
Compact SPICE model extraction and validation methodology.