558
21 Diodes
where w = x n + x p is the total width of the depletion layer. The elimination of E m from (21.105) and
(21.108) yields
w =
2 s
e
N A + N D
N A N D
V bi = x n + x p ;
(21.109)
the two parts of the depletion layer are given by
x n =
N A
N A + N D
2 s
e
N A + N D
N A N D
V bi
(21.110a)
x p =
N D
N A + N D
2 s
e
N A + N D
N A N D
V bi .
(21.110b)
For p
+ n and n
+ p junctions, the width of the depletion layer is determined by the lowly doped side of
the junction
w =
2 s
e N B
V bi ,
(21.111)
where N B denotes the doping of the lowly doped side, i.e. N A for a n
+ p diode and N D for a p
+ n diode.
If the spatial variation of the majority carrier density is considered in more detail (and for finite
temperature, cf. (21.13)), an additional term −2kT /e = −2/β is added [1757] to V bi
w =
2 s
e
N A + N D
N A N D
V bi − V − 2β −1
.
(21.112)
Also, the external bias V has been included in the formula. If w 0 denotes the depletion layer width at
zero bias, the depletion layer width for a given voltage V can be written as
w(V ) = w 0
1 −
V
V bi − 2/β
≈ w 0
1 −
V
V bi
.
(21.113)
Using the Debye length (cf. (21.85b))
L D =
s kT
e 2 N B
,
(21.114)
the depletion layer width for a one-sided diode can be written as (with β = e/kT )
w = L D
2 (βV bi − βV − 2) .
(21.115)
The Debye length is a function of the doping level and is shown for Si in Fig. 21.43. For a doping
level of 10
16 cm
−3 the Debye length in Si is 40 nm at room temperature. For one-sided junctions the
depletion layer width is about 6 L D for Ge, 8 L D for Si and 10 L D for GaAs.
The external bias is counted positive if the ‘+’ (‘−’) pole is at the p-side (n-side). The reverse voltage
has opposite polarity. If a reverse bias is applied, the depletion layer width is increased (Fig. 21.44).