546
21 Diodes
poly-Si
Si
Fig. 21.29 High-resolution transmission electron microscopy image of a 1.6-nm thick gate oxide between poly-Si (cf.
Sect. 24.5.4) and crystalline Si. From [1756]
(a)
(b)
Fig. 21.30 Band diagram of an ideal MIS diode with a n- and b p-type semiconductor at external bias V = 0. The
insulator (‘i’) thickness is d as labeled. The dash-dotted line represents the intrinsic Fermi level E i
e B = E i − E F =
E C + E V
2
+
kT
2
ln
N V
N C
−
E V − kT ln
N A
N V
=
E g
2
+ kT ln
N A
√
N C N V
= kT ln
N A
n i
.
(21.78)
When an ideal MIS diode is biased, three general cases—accumulation, depletion and inversion— can
occur (Fig. 21.35). We discuss these first for the p-type semiconductor.
Figure 21.35d shows the accumulation case for a negative voltage at the metal.
14 Part of the voltage
drops across the insulator, the rest across the semiconductor. The valence band is bent upwards towards
the Fermi level. The quasi-Fermi level in the semiconductor, however, is constant since no dc current
flows (Fig. 21.31).
15
Since the charge-carrier (hole) density depends exponentially on the energy separation E F − E V , a
charge accumulation (of holes) occurs in the (p-type) semiconductor in the vicinity of the interface to
the insulator.
14 This poling is a forward bias of the respective Schottky diode since the positive pole is at the p-type semiconductor.
15 We note that in order to reach the situations shown in Fig. 21.35 from the zero bias case of Fig. 21.30, a current must
have flowed since charge carriers are redistributed. Figure 21.35 depicts the stationary equilibrium after transient voltage
switch-on effects have subsided. The time, however, that is needed in order to reach such stationary equilibrium from
zero bias (thermal equilibrium) may be very long (e.g. days, cf. Sect. 22.3.8).
21 Diodes
poly-Si
Si
Fig. 21.29 High-resolution transmission electron microscopy image of a 1.6-nm thick gate oxide between poly-Si (cf.
Sect. 24.5.4) and crystalline Si. From [1756]
(a)
(b)
Fig. 21.30 Band diagram of an ideal MIS diode with a n- and b p-type semiconductor at external bias V = 0. The
insulator (‘i’) thickness is d as labeled. The dash-dotted line represents the intrinsic Fermi level E i
e B = E i − E F =
E C + E V
2
+
kT
2
ln
N V
N C
−
E V − kT ln
N A
N V
=
E g
2
+ kT ln
N A
√
N C N V
= kT ln
N A
n i
.
(21.78)
When an ideal MIS diode is biased, three general cases—accumulation, depletion and inversion— can
occur (Fig. 21.35). We discuss these first for the p-type semiconductor.
Figure 21.35d shows the accumulation case for a negative voltage at the metal.
14 Part of the voltage
drops across the insulator, the rest across the semiconductor. The valence band is bent upwards towards
the Fermi level. The quasi-Fermi level in the semiconductor, however, is constant since no dc current
flows (Fig. 21.31).
15
Since the charge-carrier (hole) density depends exponentially on the energy separation E F − E V , a
charge accumulation (of holes) occurs in the (p-type) semiconductor in the vicinity of the interface to
the insulator.
14 This poling is a forward bias of the respective Schottky diode since the positive pole is at the p-type semiconductor.
15 We note that in order to reach the situations shown in Fig. 21.35 from the zero bias case of Fig. 21.30, a current must
have flowed since charge carriers are redistributed. Figure 21.35 depicts the stationary equilibrium after transient voltage
switch-on effects have subsided. The time, however, that is needed in order to reach such stationary equilibrium from
zero bias (thermal equilibrium) may be very long (e.g. days, cf. Sect. 22.3.8).