354
12 Heterostructures
Fig. 12.3 a AFM images of an as-received ZnO wafer, exhibiting small terraces and nm deep scratches from polishing.
(b, c) Two ZnO (000 ¯
1) wafers with vicinal surfaces after thermal treatment (1000 ◦ C for 2 h in O 2 ), exhibiting atomically
flat terraces with c/2 monoatomic step heights. Two different substrates with different off-cut (misorientation direction
and angle) are shown. Adapted from [1122]
(a)
(b)
Fig. 12.4 Cross-sectional TEM of MBE-grown Al x Ga 1−x As/GaAs heterostructures for (a) x = 0.41 and (b) x = 1.0.
Using an AlAs/GaAs superlattice an excellent flattening of substrate roughness is achieved. From [1123]
an elaborate cleaning and polishing process. Silicon processes [1115, 1116] are based on the RCA
cleaning procedure [1117] and the related Shiraki etch [1118] and can achieve clean, atomically flat
surfaces [1119]. III-V semiconductors are typically prepared using a polishing etch [1120, 1121], often
solutions containing bromine. It is possible to create compound semiconductor surfaces that exhibit
large, essentially monoatomically flat terraces between individual surface steps. Polishing or other
surface damage can also be removed prior to epitaxy with thermal (Fig. 12.3) or ion beam treatments.
One prerequisite for making high-quality heterostructures with thin layers is a flat surface. Even if
the polished substrate is not perfect, flat interfaces can be achieved with the growth of appropriate superlattice buffer layers (Fig. 12.4). Roughness can exist on all length scales and is typically investigated
using atomic force microscopy scans.
High throughput demands and the advent of multi-wafer reactors make prior cleaning and etching procedures tedious. For this purpose, substrates for well-developed material systems are offered
‘epiready’. Epiready wafers are often covered with a very thin protective film that can be released using
a thermal treatment at or below typical growth temperature in the growth reactor immediately prior to
epitaxy. The protective film separates the polished semiconductor wafer from the ambient. Examples
are a few monolayers of arsenic on GaAs or two monolayers GaN on SiC. However, the suitability of
a purchased substrate may depend on the duration and conditions of its storage.
12 Heterostructures
Fig. 12.3 a AFM images of an as-received ZnO wafer, exhibiting small terraces and nm deep scratches from polishing.
(b, c) Two ZnO (000 ¯
1) wafers with vicinal surfaces after thermal treatment (1000 ◦ C for 2 h in O 2 ), exhibiting atomically
flat terraces with c/2 monoatomic step heights. Two different substrates with different off-cut (misorientation direction
and angle) are shown. Adapted from [1122]
(a)
(b)
Fig. 12.4 Cross-sectional TEM of MBE-grown Al x Ga 1−x As/GaAs heterostructures for (a) x = 0.41 and (b) x = 1.0.
Using an AlAs/GaAs superlattice an excellent flattening of substrate roughness is achieved. From [1123]
an elaborate cleaning and polishing process. Silicon processes [1115, 1116] are based on the RCA
cleaning procedure [1117] and the related Shiraki etch [1118] and can achieve clean, atomically flat
surfaces [1119]. III-V semiconductors are typically prepared using a polishing etch [1120, 1121], often
solutions containing bromine. It is possible to create compound semiconductor surfaces that exhibit
large, essentially monoatomically flat terraces between individual surface steps. Polishing or other
surface damage can also be removed prior to epitaxy with thermal (Fig. 12.3) or ion beam treatments.
One prerequisite for making high-quality heterostructures with thin layers is a flat surface. Even if
the polished substrate is not perfect, flat interfaces can be achieved with the growth of appropriate superlattice buffer layers (Fig. 12.4). Roughness can exist on all length scales and is typically investigated
using atomic force microscopy scans.
High throughput demands and the advent of multi-wafer reactors make prior cleaning and etching procedures tedious. For this purpose, substrates for well-developed material systems are offered
‘epiready’. Epiready wafers are often covered with a very thin protective film that can be released using
a thermal treatment at or below typical growth temperature in the growth reactor immediately prior to
epitaxy. The protective film separates the polished semiconductor wafer from the ambient. Examples
are a few monolayers of arsenic on GaAs or two monolayers GaN on SiC. However, the suitability of
a purchased substrate may depend on the duration and conditions of its storage.