58
3 SAMPA Chip Implementation
Table 3.3 BC1 baseline correction and subtraction modes. Legend: din : data input (samples);
f(t) : pattern data; FPD : fixed pedestal data; VPD : variable pedestal data; f(din) : converted data
Modes of operation
Main configurations
din - FPD
din - f(t)
(din - VPD) -
FPD
(din - VPD) -
f(t)
Subtraction
mode
Fixed
x
x
Timedependent
x
x
Variable
x
x
Conversion mode
Test mode
Modes of operation
Main configurations
f(din) - FPD
f(din - VPD) -
FPD
f(t) - FPD
Subtraction
mode
Fixed
x
x
x
Timedependent
Variable
x
Conversion mode
x
x
Test mode
x
also that the 10-bit data stored in the memory can, at the output of the memory, be
shifted to adapt to the 13-bit data in the data pipeline. It can either be 9 bits plus a sign
bit, 10 bits, 9 bits plus 1 bit precision or 8 bits plus 2 bits precision. This provides
the possibility to enter a more precise baseline value than previously where it was
fixed at 10 bits.
The usages previously mentioned allow for three different modes of operation:
subtraction mode, conversion mode and test mode. Some of these modes of operation
can be combined allowing numerous configurations of the Baseline Correction 1
(BC1) circuit. While the fixed-mode and time-dependent-mode are exclusive, any of
them can be combined with the self-calibrated mode as shown in Table 3.3.
The memory can be accessed through the I
2 C, for both read and write, as long as
the filter is not in a mode where the memory is being used in the processing chain.
In general, for this filter and the others discussed in this thesis, the adders that are
used have been altered from how they were used in the previous devices to saturate
instead of rolling over when overflowing. This should provide a more accurate value
in extreme cases.
3 SAMPA Chip Implementation
Table 3.3 BC1 baseline correction and subtraction modes. Legend: din : data input (samples);
f(t) : pattern data; FPD : fixed pedestal data; VPD : variable pedestal data; f(din) : converted data
Modes of operation
Main configurations
din - FPD
din - f(t)
(din - VPD) -
FPD
(din - VPD) -
f(t)
Subtraction
mode
Fixed
x
x
Timedependent
x
x
Variable
x
x
Conversion mode
Test mode
Modes of operation
Main configurations
f(din) - FPD
f(din - VPD) -
FPD
f(t) - FPD
Subtraction
mode
Fixed
x
x
x
Timedependent
Variable
x
Conversion mode
x
x
Test mode
x
also that the 10-bit data stored in the memory can, at the output of the memory, be
shifted to adapt to the 13-bit data in the data pipeline. It can either be 9 bits plus a sign
bit, 10 bits, 9 bits plus 1 bit precision or 8 bits plus 2 bits precision. This provides
the possibility to enter a more precise baseline value than previously where it was
fixed at 10 bits.
The usages previously mentioned allow for three different modes of operation:
subtraction mode, conversion mode and test mode. Some of these modes of operation
can be combined allowing numerous configurations of the Baseline Correction 1
(BC1) circuit. While the fixed-mode and time-dependent-mode are exclusive, any of
them can be combined with the self-calibrated mode as shown in Table 3.3.
The memory can be accessed through the I
2 C, for both read and write, as long as
the filter is not in a mode where the memory is being used in the processing chain.
In general, for this filter and the others discussed in this thesis, the adders that are
used have been altered from how they were used in the previous devices to saturate
instead of rolling over when overflowing. This should provide a more accurate value
in extreme cases.