2.3 Design Requirements
21
minimizes the amount of communication lines going to and from the SAMPA. In case
of the MCH, this is beneficial as several devices are sharing a cable with a limited
amount of communication lines. The GBT-SCA provides an I
2 C master that can
operate at 1 Mbps, which should be sufficiently fast enough. If faster communication
is needed, another option is to include the outgoing slow-control data in the serial
uplink path and add an extra serial input for reception of slow-control data. Since
the differential serial-downlink can also be multidrop connected to several devices,
it does not require more communication lines than the I
2 C solution.
2.3.3.7 Reliability
Since the electronics will be located in a radiation area with limited access, there is a
need for high reliability of the equipment to avoid downtime and loss of experimental
data. Special care needs to be taken to protect the system against potential corruption
of control and data registers caused by radiation-induced Single Event Effects (SEE).
This also includes self-recovery in case of unforeseen errors and the ability to turn
off broken channels to avoid that they transmit garbage data.
2.3.3.8 Design for Testability
The total number of chips required to cover all the channels of the TPC and MCH
is about 51 000. Accounting for about 15% in spares and 30% in loss due to yield
problems, this totals about 83 000 chips. As multiple chips will be mounted on the
same front-end board, the yield of the front-end boards will be low if significant
amounts of chips with manufacturing defects are mounted. For the TPC, with five
chips on the front-end board, the probability of having a board with one or more chips
with manufacturing defects is 41% if the probability of a chip having a manufacturing
defect is 10%. The high number of chips that need to be tested requires an automatic
testing procedure. The combined test time for a PASA and ALTRO chip for the
original commissioning of the TPC was about 2 min, which if applied to the SAMPA
chip would mean 3.8 months of continuous testing without parallelization. Effective
ways of testing the device is therefore necessary. A possible option is to do additional
testing at the manufacturing plant on the wafer level with automated test equipment
to filter out bad devices before they are packaged. This comes at an additional cost,
though it saves some time on the final testing, as the number of devices that needs
to be tested at the packaged level will be fewer. Additionally there is also some cost
savings as the number of devices that needs to be packaged is lower.
21
minimizes the amount of communication lines going to and from the SAMPA. In case
of the MCH, this is beneficial as several devices are sharing a cable with a limited
amount of communication lines. The GBT-SCA provides an I
2 C master that can
operate at 1 Mbps, which should be sufficiently fast enough. If faster communication
is needed, another option is to include the outgoing slow-control data in the serial
uplink path and add an extra serial input for reception of slow-control data. Since
the differential serial-downlink can also be multidrop connected to several devices,
it does not require more communication lines than the I
2 C solution.
2.3.3.7 Reliability
Since the electronics will be located in a radiation area with limited access, there is a
need for high reliability of the equipment to avoid downtime and loss of experimental
data. Special care needs to be taken to protect the system against potential corruption
of control and data registers caused by radiation-induced Single Event Effects (SEE).
This also includes self-recovery in case of unforeseen errors and the ability to turn
off broken channels to avoid that they transmit garbage data.
2.3.3.8 Design for Testability
The total number of chips required to cover all the channels of the TPC and MCH
is about 51 000. Accounting for about 15% in spares and 30% in loss due to yield
problems, this totals about 83 000 chips. As multiple chips will be mounted on the
same front-end board, the yield of the front-end boards will be low if significant
amounts of chips with manufacturing defects are mounted. For the TPC, with five
chips on the front-end board, the probability of having a board with one or more chips
with manufacturing defects is 41% if the probability of a chip having a manufacturing
defect is 10%. The high number of chips that need to be tested requires an automatic
testing procedure. The combined test time for a PASA and ALTRO chip for the
original commissioning of the TPC was about 2 min, which if applied to the SAMPA
chip would mean 3.8 months of continuous testing without parallelization. Effective
ways of testing the device is therefore necessary. A possible option is to do additional
testing at the manufacturing plant on the wafer level with automated test equipment
to filter out bad devices before they are packaged. This comes at an additional cost,
though it saves some time on the final testing, as the number of devices that needs
to be tested at the packaged level will be fewer. Additionally there is also some cost
savings as the number of devices that needs to be packaged is lower.