2.3 Design Requirements
19
2.3.3 Common Requirements
As both the TPC and MCH operate in the same ALICE environment and they both
plan to utilize the GBTx and GBT-SCA devices in conjunction with the CRU readout
electronics, many of their requirements for the SAMPA design will be the same. This
section presents the common requirements and the next sections present the TPC and
MCH specific requirements respectively.
2.3.3.1 Technology
CERN has experience in previous designs of low noise radiation tolerant devices in
the IBM 130 nm technology, like in the design of the predecessor chip S-ALTRO.
However, the 130 nm technology is becoming an ageing process and as IBM decided
to sell off its foundry business to GlobalFoundries, the future of the process is somewhat uncertain. The design will instead be done in a TSMC process. TSMC provide
a 130 nm technology and a 65 nm technology in their advanced process node. The
130 nm technology was chosen for this design as there are generally more problems
designing analogue circuits in lower process nodes, e.g. problems with higher noise,
lower voltage headroom, transistor matching, radiation sensitivity, etc. Even though
there are benefits of lower size, higher clock speeds and lower power. It has though
been later shown that the 65 nm process node also is suitable for design of sensitive
front-end electronics [19, 20].
2.3.3.2 Noise
The simulated TPC SAMPA noise requirements are the same as the simulated noise
for the PASA [18], though at a higher gain which gives some extra headroom. The
TPC aims at retaining the same system noise of 670 e as of today. The challenge
is that the digital and ADC now are integrated together with the sensitive analogue
electronics. Additionally the digital section is constantly processing and sending
data off-chip, while the analogue section is acquiring data. The S-ALTRO proved
that it is possible to integrate digital and analogue and still reach 550 e [6], measured
un-bonded and without input capacitance, so the requirement is viable. The use of
low signal swing differential lines for the data transmission and taking precautions
in shielding the interface between the digital and analogue domain should satisfy the
second concern.
In the case of the MCH, due to their low gain, the noise will be dominated by
the resolution and accuracy of the ADC. The noise requirement of 1000 e is equal
to 0.64 mV at 4 mV/fC, which is 0.3 LSB. Depending on if the baseline is in the
transition part between two codes or between two transition points, the noise will
vary between no noise and 0.5 LSB noise.
19
2.3.3 Common Requirements
As both the TPC and MCH operate in the same ALICE environment and they both
plan to utilize the GBTx and GBT-SCA devices in conjunction with the CRU readout
electronics, many of their requirements for the SAMPA design will be the same. This
section presents the common requirements and the next sections present the TPC and
MCH specific requirements respectively.
2.3.3.1 Technology
CERN has experience in previous designs of low noise radiation tolerant devices in
the IBM 130 nm technology, like in the design of the predecessor chip S-ALTRO.
However, the 130 nm technology is becoming an ageing process and as IBM decided
to sell off its foundry business to GlobalFoundries, the future of the process is somewhat uncertain. The design will instead be done in a TSMC process. TSMC provide
a 130 nm technology and a 65 nm technology in their advanced process node. The
130 nm technology was chosen for this design as there are generally more problems
designing analogue circuits in lower process nodes, e.g. problems with higher noise,
lower voltage headroom, transistor matching, radiation sensitivity, etc. Even though
there are benefits of lower size, higher clock speeds and lower power. It has though
been later shown that the 65 nm process node also is suitable for design of sensitive
front-end electronics [19, 20].
2.3.3.2 Noise
The simulated TPC SAMPA noise requirements are the same as the simulated noise
for the PASA [18], though at a higher gain which gives some extra headroom. The
TPC aims at retaining the same system noise of 670 e as of today. The challenge
is that the digital and ADC now are integrated together with the sensitive analogue
electronics. Additionally the digital section is constantly processing and sending
data off-chip, while the analogue section is acquiring data. The S-ALTRO proved
that it is possible to integrate digital and analogue and still reach 550 e [6], measured
un-bonded and without input capacitance, so the requirement is viable. The use of
low signal swing differential lines for the data transmission and taking precautions
in shielding the interface between the digital and analogue domain should satisfy the
second concern.
In the case of the MCH, due to their low gain, the noise will be dominated by
the resolution and accuracy of the ADC. The noise requirement of 1000 e is equal
to 0.64 mV at 4 mV/fC, which is 0.3 LSB. Depending on if the baseline is in the
transition part between two codes or between two transition points, the noise will
vary between no noise and 0.5 LSB noise.