12
2 Front-End Electronics
retained the design of the ALTRO intact, with some minor improvements to the
digital signal conditioning.
For the third run period of the LHC, the ATLAS CMS
1 GEM detector is also planning to update its front-end electronics. Early in the research phase for the upgrade of
the CMS GEM detector, a new front-end chip called the Gas detector digital Signal
Processor (GdSP) [10] was proposed and evaluated. It was planned to consist of
64 or 128 channels, with accompanying ADCs, and with a reworked version of the
baseline filtering chain from the S-ALTRO in addition to a new digital readout compatible with the Gigabit Transceiver (GBTx) chip [11]. Preliminary analysis work
and improvements were done on the filtering and compression architecture before the
project decided to use a comparator instead of an ADC, and also to only read out time
over threshold measurements, making the baseline filtering capability unneeded.
The SAMPA project bases its analogue front-end on the design of the PASA chip
and the filter and zero suppression compression from all of the previous developments.
2.1.1 PASA
The PASA ASIC is a 16-channel preamplifier and shaper chip for use with gaseous
detectors. The device was originally custom designed for the ALICE TPC detector [1] and is fabricated in an Austria Micro Systems (AMS) 0.35 µm CMOS technology. The manufactured design has a shaping time of 190 ns, a conversion gain
of 12.8 mV/fC @ 12 pF, a noise of 385 e @ 12 pF and it accepts positive polarity
input signals. Together with the ALTRO chip, it was measured to have an overall
system noise of 710 e when installed in the TPC detector. Table 2.1 lists the tested
specifications for the design.
The block diagram of the processing chain for a single channel is shown in Fig. 2.1.
Each channel consists of a positive polarity Charge Sensitive Amplifier (CSA) with
a capacitive feedback C f and a resistive feedback R f (M f ) connected in parallel.
The input charge is integrated through the feedback capacitor C f , while the parallel
resistor R f is used to discharge the capacitor leading the signal to the baseline level
with an exponential tail. Following the CSA is a Pole-Zero Cancellation network
to remove undershoot in the tail of the signal. The signal is then further amplified
and shaped through a fourth-order semi-Gaussian shaper. The final stage adapts the
signal levels to match the input of the ALTRO ADC.
1 A Toroidal LHC ApparatuS Compact Muon Solenoid.
2 Front-End Electronics
retained the design of the ALTRO intact, with some minor improvements to the
digital signal conditioning.
For the third run period of the LHC, the ATLAS CMS
1 GEM detector is also planning to update its front-end electronics. Early in the research phase for the upgrade of
the CMS GEM detector, a new front-end chip called the Gas detector digital Signal
Processor (GdSP) [10] was proposed and evaluated. It was planned to consist of
64 or 128 channels, with accompanying ADCs, and with a reworked version of the
baseline filtering chain from the S-ALTRO in addition to a new digital readout compatible with the Gigabit Transceiver (GBTx) chip [11]. Preliminary analysis work
and improvements were done on the filtering and compression architecture before the
project decided to use a comparator instead of an ADC, and also to only read out time
over threshold measurements, making the baseline filtering capability unneeded.
The SAMPA project bases its analogue front-end on the design of the PASA chip
and the filter and zero suppression compression from all of the previous developments.
2.1.1 PASA
The PASA ASIC is a 16-channel preamplifier and shaper chip for use with gaseous
detectors. The device was originally custom designed for the ALICE TPC detector [1] and is fabricated in an Austria Micro Systems (AMS) 0.35 µm CMOS technology. The manufactured design has a shaping time of 190 ns, a conversion gain
of 12.8 mV/fC @ 12 pF, a noise of 385 e @ 12 pF and it accepts positive polarity
input signals. Together with the ALTRO chip, it was measured to have an overall
system noise of 710 e when installed in the TPC detector. Table 2.1 lists the tested
specifications for the design.
The block diagram of the processing chain for a single channel is shown in Fig. 2.1.
Each channel consists of a positive polarity Charge Sensitive Amplifier (CSA) with
a capacitive feedback C f and a resistive feedback R f (M f ) connected in parallel.
The input charge is integrated through the feedback capacitor C f , while the parallel
resistor R f is used to discharge the capacitor leading the signal to the baseline level
with an exponential tail. Following the CSA is a Pole-Zero Cancellation network
to remove undershoot in the tail of the signal. The signal is then further amplified
and shaped through a fourth-order semi-Gaussian shaper. The final stage adapts the
signal levels to match the input of the ALTRO ADC.
1 A Toroidal LHC ApparatuS Compact Muon Solenoid.