1.2 LHC Run 3 Upgrades
9
expected rate of 50 kHz. It was found that it is not feasible to upgrade the MTR
for these rates and the data from the MTR will instead be used offline for hadron
rejection.
Lacking a suitable trigger source, the MCH will instead read out data continuously,
requiring a redesign of the front-end card and readout electronics.
1.3 Primary Objective and Main Contributions
The SAMPA project started in the winter of 2012 with the early design of the frontend, and later, the early prototype of the ADC, by Hugo Hernandez of the Electrical
Engineering-Polytechnical School, University of São Paulo, Brazil. Heitor Guzzo
Neves started initial development for the first prototype of the digital design for the
SAMPA ASIC, primarily based on the Super ALTRO (S-ALTRO), in early 2013. He
was later assisted by Bruno Sanchez, both of the Electrical Engineering-Polytechnical
School, University of São Paulo, Brazil. I joined the project in mid-2013 for firmware
verification and testing, as described in Chap. 4. Together with Alex Kluge, the digital
and system level specifications for a 32 channel mixed-signal front-end chip meeting
the requirements for both TPC and MCH detectors, together with the architectural
design of the digital design was defined in late 2013, as presented in Sect. 2.4 and
Chap. 3 respectively. Heitor left the project in late 2014, and I took over the responsibility of the development of the design. Optimization of the S-ALTRO filters for more
flexibility and higher reliability in the SAMPA, in combination with the testbenches
needed for their verification, was done in collaboration with Bruno. An exception is
the Baseline Correction 3 (BC3) filter which was developed by Konstantin Münning
of the Universität Bonn in collaboration with Bruno. Coding of the base I
2 C module
used by the design was done by Sandro Bonacini from CERN. However, the design
was modified for readability and full test framework was added. Furthermore, my
development of an efficient readout scheme to meet bandwidth requirements for the
system is presented in Sect. 2.4.3, my design and implementation of a high speed
data acquisition and analysis system for use in characterization of the SAMPA ASIC
presented in Sect. 4.2, and the experimental characterization of the SAMPA ASIC is
presented in Sect. 4.3.
Overall, the development of the SAMPA ASIC has been orchestrated by the
Electrical Engineering-Polytechnical School, University of São Paulo, Brazil.
References
1. The ALICE Collaboration, “The ALICE Experiment at the CERN LHC,” Journal of Instrumentation, vol. 3, no. 08, p. S08002, Aug 2008.
2. The ALICE Collaboration, “ALICE Dimuon forward spectrometer,” CERN, Tech. Design Rep.
CERN-LHCC-1999-022, 1999. [Online]. Available: http://cds.cern.ch/record/401974.
9
expected rate of 50 kHz. It was found that it is not feasible to upgrade the MTR
for these rates and the data from the MTR will instead be used offline for hadron
rejection.
Lacking a suitable trigger source, the MCH will instead read out data continuously,
requiring a redesign of the front-end card and readout electronics.
1.3 Primary Objective and Main Contributions
The SAMPA project started in the winter of 2012 with the early design of the frontend, and later, the early prototype of the ADC, by Hugo Hernandez of the Electrical
Engineering-Polytechnical School, University of São Paulo, Brazil. Heitor Guzzo
Neves started initial development for the first prototype of the digital design for the
SAMPA ASIC, primarily based on the Super ALTRO (S-ALTRO), in early 2013. He
was later assisted by Bruno Sanchez, both of the Electrical Engineering-Polytechnical
School, University of São Paulo, Brazil. I joined the project in mid-2013 for firmware
verification and testing, as described in Chap. 4. Together with Alex Kluge, the digital
and system level specifications for a 32 channel mixed-signal front-end chip meeting
the requirements for both TPC and MCH detectors, together with the architectural
design of the digital design was defined in late 2013, as presented in Sect. 2.4 and
Chap. 3 respectively. Heitor left the project in late 2014, and I took over the responsibility of the development of the design. Optimization of the S-ALTRO filters for more
flexibility and higher reliability in the SAMPA, in combination with the testbenches
needed for their verification, was done in collaboration with Bruno. An exception is
the Baseline Correction 3 (BC3) filter which was developed by Konstantin Münning
of the Universität Bonn in collaboration with Bruno. Coding of the base I
2 C module
used by the design was done by Sandro Bonacini from CERN. However, the design
was modified for readability and full test framework was added. Furthermore, my
development of an efficient readout scheme to meet bandwidth requirements for the
system is presented in Sect. 2.4.3, my design and implementation of a high speed
data acquisition and analysis system for use in characterization of the SAMPA ASIC
presented in Sect. 4.2, and the experimental characterization of the SAMPA ASIC is
presented in Sect. 4.3.
Overall, the development of the SAMPA ASIC has been orchestrated by the
Electrical Engineering-Polytechnical School, University of São Paulo, Brazil.
References
1. The ALICE Collaboration, “The ALICE Experiment at the CERN LHC,” Journal of Instrumentation, vol. 3, no. 08, p. S08002, Aug 2008.
2. The ALICE Collaboration, “ALICE Dimuon forward spectrometer,” CERN, Tech. Design Rep.
CERN-LHCC-1999-022, 1999. [Online]. Available: http://cds.cern.ch/record/401974.