4.3 Validation and Testing
123
triggers on the input lines, the input on the SAMPA would incorrectly toggle during
a transition, creating incorrectly received data, particularly at the I
2 C stop bit. The
SAMPA has a built-in watchdog that resets the I
2 C module in case it does not receive
a new transition on the line within 13 µs, but due to a design error this did not apply to
the circuitry that detects the start and stop-messages and the design was stuck waiting
for a proper stop message. As the issue was discovered after the final v3 production,
it was solved by adding an I
2 C buffer (Texas Instruments TCA9803 [31]) in front of
the SAMPA to reshape the signal and avoid the issue. The TCA9803 was irradiated
with a 200 MeV proton beam to 50 kRad without errors [32].
The STAR front-end card has no special interfacing requirements, but in contrast
to the other detectors, it uses a triggered readout mode with a shorter time window.
During testing, an issue was found that was only present in the triggered mode, where
the memory pointers in the ring buffer came out of sync between the header and data
memory, causing incorrect payload data to be sent for a given header. The issue is
corrected in v3 and a workaround can be applied for v2 devices.
References
1. Bitvis. (2017) Bitvis utility library. [Online]. Available: http://bitvis.no/products/bitvis-utilitylibrary/.
2. Cadence. (2017) Incisive Enterprise Simulator. [Online]. Available: https://www.cadence.
com/content/cadence-www/global/en_US/home/tools/system-design-and-verification/
simulation-and-testbench-verification/incisive-enterprise-simulator.html.
3. Mentor. (2017) Questa Advanced Simulator. [Online]. Available: https://www.mentor.com/
products/fv/questa/.
4. A. Velure and B. Sanches, SAMPA Specification, 2017.
5. S. M. Mahmood, “Exploring Single Event Effects in SAMPA ASIC for Time Projection Chamber (TPC) and Muon CHamber (MCH) detectors in A Large Ion Collider Experiment (ALICE),”
Ph.D. dissertation, University of Oslo, Oslo, Norway, 2019, to be published.
6. S. Sutherland and DonMills, Verilog and SystemVerilog Gotchas, 2007.
7. W. Snyder. (2017) Verilator. [Online]. Available: https://www.veripool.org/wiki/verilator.
8. Mentor. (2017) HDL Designer. [Online]. Available: https://www.mentor.com/products/fpga/
hdl_design/hdl_designer_series/.
9. Cadence. (2017) Incisive Formal Verifier. [Online]. Available: https://www.cadence.com/
content/cadence-www/global/en_US/home/tools/system-design-and-verification/formaland-static-verification/incisive-formal-verification-platform/incisive-formal-verifier.html.
10. Mentor. (2017) FormalPro. [Online]. Available: https://www.mentor.com/products/fv/
formalpro/.
11. Cadence. (2017) Conformal Equivalence Checker. [Online]. Available: https://www.
cadence.com/content/cadence-www/global/en_US/home/tools/digital-design-and-signoff/
equivalence-checking/conformal-equivalence-checker.html.
12. The ALICE Collaboration, “Upgrade of the ALICE read-out and trigger system,” CERN, Tech.
Design Rep. CERN-LHCC-2013-019, ALICE-TDR-015, 2013. [Online]. Available: http://cds.
cern.ch/record/1603472.
13. Cadence. (2018) Modus. [Online]. Available: https://www.cadence.com/content/cadencewww/global/en_US/home/tools/digital-design-and-signoff/test/modus-test.html.
14. C. E. Cummings, “Clock domain crossing (CDC) design & verification techniques using SystemVerilog,” in Synopsis User Group Meeting, 2008.
123
triggers on the input lines, the input on the SAMPA would incorrectly toggle during
a transition, creating incorrectly received data, particularly at the I
2 C stop bit. The
SAMPA has a built-in watchdog that resets the I
2 C module in case it does not receive
a new transition on the line within 13 µs, but due to a design error this did not apply to
the circuitry that detects the start and stop-messages and the design was stuck waiting
for a proper stop message. As the issue was discovered after the final v3 production,
it was solved by adding an I
2 C buffer (Texas Instruments TCA9803 [31]) in front of
the SAMPA to reshape the signal and avoid the issue. The TCA9803 was irradiated
with a 200 MeV proton beam to 50 kRad without errors [32].
The STAR front-end card has no special interfacing requirements, but in contrast
to the other detectors, it uses a triggered readout mode with a shorter time window.
During testing, an issue was found that was only present in the triggered mode, where
the memory pointers in the ring buffer came out of sync between the header and data
memory, causing incorrect payload data to be sent for a given header. The issue is
corrected in v3 and a workaround can be applied for v2 devices.
References
1. Bitvis. (2017) Bitvis utility library. [Online]. Available: http://bitvis.no/products/bitvis-utilitylibrary/.
2. Cadence. (2017) Incisive Enterprise Simulator. [Online]. Available: https://www.cadence.
com/content/cadence-www/global/en_US/home/tools/system-design-and-verification/
simulation-and-testbench-verification/incisive-enterprise-simulator.html.
3. Mentor. (2017) Questa Advanced Simulator. [Online]. Available: https://www.mentor.com/
products/fv/questa/.
4. A. Velure and B. Sanches, SAMPA Specification, 2017.
5. S. M. Mahmood, “Exploring Single Event Effects in SAMPA ASIC for Time Projection Chamber (TPC) and Muon CHamber (MCH) detectors in A Large Ion Collider Experiment (ALICE),”
Ph.D. dissertation, University of Oslo, Oslo, Norway, 2019, to be published.
6. S. Sutherland and DonMills, Verilog and SystemVerilog Gotchas, 2007.
7. W. Snyder. (2017) Verilator. [Online]. Available: https://www.veripool.org/wiki/verilator.
8. Mentor. (2017) HDL Designer. [Online]. Available: https://www.mentor.com/products/fpga/
hdl_design/hdl_designer_series/.
9. Cadence. (2017) Incisive Formal Verifier. [Online]. Available: https://www.cadence.com/
content/cadence-www/global/en_US/home/tools/system-design-and-verification/formaland-static-verification/incisive-formal-verification-platform/incisive-formal-verifier.html.
10. Mentor. (2017) FormalPro. [Online]. Available: https://www.mentor.com/products/fv/
formalpro/.
11. Cadence. (2017) Conformal Equivalence Checker. [Online]. Available: https://www.
cadence.com/content/cadence-www/global/en_US/home/tools/digital-design-and-signoff/
equivalence-checking/conformal-equivalence-checker.html.
12. The ALICE Collaboration, “Upgrade of the ALICE read-out and trigger system,” CERN, Tech.
Design Rep. CERN-LHCC-2013-019, ALICE-TDR-015, 2013. [Online]. Available: http://cds.
cern.ch/record/1603472.
13. Cadence. (2018) Modus. [Online]. Available: https://www.cadence.com/content/cadencewww/global/en_US/home/tools/digital-design-and-signoff/test/modus-test.html.
14. C. E. Cummings, “Clock domain crossing (CDC) design & verification techniques using SystemVerilog,” in Synopsis User Group Meeting, 2008.