4.1 Functional Verification of the Digital Design
95
during hardware testing of v2 that were not caught during simulation, because the
functional coverage was not exhaustive or high enough.
For the design of the SAMPA v2, the design was primarily tested using a clear
box approach, as opposed to a black box approach, where the designer of the tests
also was the designer of the circuitry to be tested. The benefit of this approach is that
the needed coverage is reached faster since the designer knows which specific issues
and problems to test for, but the designer may, on the other hand, have an obstructed
view on other potential issues due to having pre-knowledge from the design phase.
To provide a consistent testing environment, this design uses the Bitvis Utility
Library [1], which is an open source VHDL testbench infrastructure library. The
library reduces the workload needed to design and analyse tests by providing a
structured uniform logging mechanism. It also provides methods for checking and
reporting of signals and transactions with verbosity and severity handling. The testbenches are compatible with and can be run on both Cadence Incisive Simulator [2]
and Mentor Questa Sim [3].
To aid in code review and to help visualize the designed implementation, all the
main modules have additionally been drawn schematically and are available in [4].
Based on the results of this process, various pieces of redundant or unnecessary
circuitry were discovered and removed between v2 and v3.
The design has been functionally verified through simulation with TMR protection
enabled, but verification of the correctness of the TMR implementation and its ability
to correct for error has not been done in simulation due to lack of suitable tools and
the complexity involved in doing the verification manually. Verification has instead
been done in hardware; see Sect. 4.3.4 and [5].
4.1.1 Tool Based Analysis
To detect all problematic edge cases in a design, the amount of time needed for simulation grows rapidly as the design grows in complexity. To alleviate this, certain tools
are available which runs static analysis of the design code to detect potential issues.
Instead of simulating the design, the tools use techniques like data flow analysis,
control flow analysis, lexical analysis, and formal analysis to find potential issues.
4.1.1.1 Static Code Analysis
The RTL code for the digital design has been written in Verilog with some enhancements from System-Verilog. Verilog is a loosely typed language, which means that
any data type can be assigned to a variable of a different type without an error or
warning being created. The benefit of this approach is that the code becomes less
verbose and easier to write, but the drawback is that it is relatively easy to make a
minor mistake that is hard to detect even with the help of simulation. There are also
certain idiosyncrasies to the language that makes it prone to produce bad code [6]. As
95
during hardware testing of v2 that were not caught during simulation, because the
functional coverage was not exhaustive or high enough.
For the design of the SAMPA v2, the design was primarily tested using a clear
box approach, as opposed to a black box approach, where the designer of the tests
also was the designer of the circuitry to be tested. The benefit of this approach is that
the needed coverage is reached faster since the designer knows which specific issues
and problems to test for, but the designer may, on the other hand, have an obstructed
view on other potential issues due to having pre-knowledge from the design phase.
To provide a consistent testing environment, this design uses the Bitvis Utility
Library [1], which is an open source VHDL testbench infrastructure library. The
library reduces the workload needed to design and analyse tests by providing a
structured uniform logging mechanism. It also provides methods for checking and
reporting of signals and transactions with verbosity and severity handling. The testbenches are compatible with and can be run on both Cadence Incisive Simulator [2]
and Mentor Questa Sim [3].
To aid in code review and to help visualize the designed implementation, all the
main modules have additionally been drawn schematically and are available in [4].
Based on the results of this process, various pieces of redundant or unnecessary
circuitry were discovered and removed between v2 and v3.
The design has been functionally verified through simulation with TMR protection
enabled, but verification of the correctness of the TMR implementation and its ability
to correct for error has not been done in simulation due to lack of suitable tools and
the complexity involved in doing the verification manually. Verification has instead
been done in hardware; see Sect. 4.3.4 and [5].
4.1.1 Tool Based Analysis
To detect all problematic edge cases in a design, the amount of time needed for simulation grows rapidly as the design grows in complexity. To alleviate this, certain tools
are available which runs static analysis of the design code to detect potential issues.
Instead of simulating the design, the tools use techniques like data flow analysis,
control flow analysis, lexical analysis, and formal analysis to find potential issues.
4.1.1.1 Static Code Analysis
The RTL code for the digital design has been written in Verilog with some enhancements from System-Verilog. Verilog is a loosely typed language, which means that
any data type can be assigned to a variable of a different type without an error or
warning being created. The benefit of this approach is that the code becomes less
verbose and easier to write, but the drawback is that it is relatively easy to make a
minor mistake that is hard to detect even with the help of simulation. There are also
certain idiosyncrasies to the language that makes it prone to produce bad code [6]. As