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could protect chips against malicious circuitry January (2015). http://spectrum.ieee.org/sem
iconductors/design/stopping-hardware-trojansin-their-tracks
94. Y. Alkabani, F. Koushanfar, M. Potkonjak, Remote activation of ICs for piracy prevention
and digital right management, in ICCAD (2007), pp. 674—677
95. IEEE standard for property specification language (psl). IEEE Std 1850–2010 (Revision of
IEEE Std 1850-2005), April (2010), pp. 1-18
96. R.S. Chakraborty, S. Bhunia, Security against hardware trojan attacks using key-based
design obfuscation. J. Elect. Test. 27(6), 767–785 (2011). https://doi.org/10.1007/s10836011-5255-2
97. Y. Alkabani, F. Koushanfar, Active hardware metering for intellectual property protection and
security, in USENIX Security Symp (2007), pp. 291—306
98. M. Banga, M. Hsiao, A region based approach for the identification of hardware trojans, in
Hardware-Oriented Security and Trust, 2008. HOST 2008. IEEE International Workshop,
June (2008), pp. 40–47
99. D. Forte, C. Bao, A. Srivastava, Temperature tracking: an innovative run-time approach
for hardware trojan detection, in Computer-Aided Design (ICCAD), 2013 IEEE/ACM
International Conference, November (2013), pp. 532–539
100. C. Lamech, R. Rad, M. Tehranipoor, J. Plusquellic, An experimental analysis of power
and delay signal-to-noise requirements for detecting trojans and methods for achieving the
required detection sensitivities. Inf. Forensics Sec. IEEE Trans. 6(3), 1170–1179 September
(2011)
101. B. Cakir B, S. Malik, Hardware trojan detection for gate-level ics using signal correlation
based clustering, Proceedings of the 2015 Design, Automation & Test in Europe Conference
& Exhibition. DATE’15 (EDA Consortium, San Jose, CA, USA 2015), 471–476. http://dl.
acm.org/citation.cfm?id=2755753.2755860
102. A. Sengupta, S. Bhadauria, Untrusted third party digital ip cores: Power-delay trade-off driven
exploration of hardware trojan secured data path during high level synthesis, in Proceedings
of the 25th Edition on Great Lakes Symposium on VLSI. R 167–172. GLSVLSI’15 (ACM,
New York, NY, USA, 2015). http://doi.acm.org/10.1145/2742060.2742061
103. X. Zhang, M. Tehranipoor, Case study: detecting hardware trojans in third-party digital
ip cores, in Hardware-Oriented Security and Trust (HOST), 2011 IEEE International
Symposium, June (2011), pp. 67–70
104. S. Bhunia, M. Abramovici, D. Agrawal, P. Bradley, M. Hsiao, J. Plusquellic, M. Tehranipoor,
Protection against hardware trojan attacks: towards a comprehensive solution. Design Test,
IEEE 30(3), 6–17, June (2013)
105. F. Hategekimana, A. Tbatou, C. Bobda, C.A. Kamhoua, K.A. Kwiat, Hardware isolation
technique for irc-based botnets detection, in International Conference on ReConFigurable
Computing and FPGAs, ReConFig 2015 (Riviera Maya, Mexico, December 7–9, 2015),
pp. 1-6. http://dx.doi.org/10.1109/ReConFig.2015.7393319
106. ARM: Trust zone January (2015). http://www.arm.com/products/processors/technologies/tru
stzone/
107. W. Venema, Isolation mechanisms for commodity applications and platforms. Tech. Rep.
RC24725(W0901–048), IBM (01 2009)
108. A. Pnueli, Special issue semantics of concurrent computation the temporal semantics of
concurrent programs. Theor. Comput. Sci. 13(1), 45–60 (1981). http://www.sciencedirect.
com/science/article/pii/0304397581901109
109. Z. Glazberg, M. Moulin, A. Orni, S. Ruah, E. Zarpas, Psl: Beyond hardware verification, in
S. Ramesh, P. Sampath P (eds.) Next Generation Design and Verification Methodologies for
Distributed Embedded Control Systems, pp. 245–260 (Springer, Netherlands, 2007). http://
dx.doi.org/10.1007/978-1-4020-6254-4_19