7.2 A Trojan-Resistant System …
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7.2 A Trojan-Resistant System-on-Chip Bus Architecture
7.2.1 Introduction to the Problem
In the work [29] by L.W Kim I.D. Villasenor and C.K. Koc, a special organization
of a Trojan-resistant system bus was examined. This system bus identifies malicious operating modes of buses associated wit Trojan circuits, reliably protects both
the entire system and the specific system SoC bus from them and communicates
information about malicious operation modes to the system CPU.
Although there are many components in the system of chip as of the moment of
publication of this book, each of which can be targeted by a potential intruder, we
are going to consider only a specific example of organizing control over the control
bus in case of identification of Trojan attacks detailed in [29]. Such a control bus that
allows the master device (e.g., a processor, various devices of direct memory access,
various communication blocks, I/O interface blocks) to have free quick access to
slave devices (memory controllers, universal asynchronous receivers–transmitters,
timers, etc.). In modern telecommunication and computation systems, where such
master device establishes coordinated mode during joint operation of all components,
this is not a difficult task. However, the attacking Trojan can force this master device
to sustain bus blocking without authorization for any arbitrary lengthy periods of
time required by the intruder. Even though the system can remain on in this case,
which is periodically communicated to the user, it will actually be locked and unable
to operate properly. The work [29] presents a version of architecture of such safe bus
that can be used both to identify the fact of a Trojan attack and to protect the systems
from Trojan attacks in real time.
We included the materials presented in [29] in our encyclopedia as close to the
original as possible due to the fact that such protection of integrated circuits from
Trojans had not been examined in literature before. In particular, this is the first work
known to us that considers the following aspects: (1) features of organizing Trojan
attacks in real time and measures of protection against such attacks in real time, (2)
SoC protection using organization of control bus architecture resistant to the Trojan.
The material in [29] was presented as follows. First of all, the authors considered features of organization of traditional single-chip system buses. After that they
described the composition of blocks of the suggested architecture of the universal
SoC bus. After that the authors presented a detailed description of the basic methods
underlying this security architecture of the SoC bus in the specific context of AMBA
bus. The end of [29] contains consideration of an interrupt handling method used
to obtain information about behavior of Trojans, which is designed to exclude the
possibility of influence of even embedded Trojans on the operation of the charged
computing system (device) by cutting off the critical connections between this system
bus and the charged IP block. Below we will present the main provisions of this
paper allowing the reader to understand the essence of this approach. If the readers
are deeply interested in the subject, they can further refer to the original paper [29].
657
7.2 A Trojan-Resistant System-on-Chip Bus Architecture
7.2.1 Introduction to the Problem
In the work [29] by L.W Kim I.D. Villasenor and C.K. Koc, a special organization
of a Trojan-resistant system bus was examined. This system bus identifies malicious operating modes of buses associated wit Trojan circuits, reliably protects both
the entire system and the specific system SoC bus from them and communicates
information about malicious operation modes to the system CPU.
Although there are many components in the system of chip as of the moment of
publication of this book, each of which can be targeted by a potential intruder, we
are going to consider only a specific example of organizing control over the control
bus in case of identification of Trojan attacks detailed in [29]. Such a control bus that
allows the master device (e.g., a processor, various devices of direct memory access,
various communication blocks, I/O interface blocks) to have free quick access to
slave devices (memory controllers, universal asynchronous receivers–transmitters,
timers, etc.). In modern telecommunication and computation systems, where such
master device establishes coordinated mode during joint operation of all components,
this is not a difficult task. However, the attacking Trojan can force this master device
to sustain bus blocking without authorization for any arbitrary lengthy periods of
time required by the intruder. Even though the system can remain on in this case,
which is periodically communicated to the user, it will actually be locked and unable
to operate properly. The work [29] presents a version of architecture of such safe bus
that can be used both to identify the fact of a Trojan attack and to protect the systems
from Trojan attacks in real time.
We included the materials presented in [29] in our encyclopedia as close to the
original as possible due to the fact that such protection of integrated circuits from
Trojans had not been examined in literature before. In particular, this is the first work
known to us that considers the following aspects: (1) features of organizing Trojan
attacks in real time and measures of protection against such attacks in real time, (2)
SoC protection using organization of control bus architecture resistant to the Trojan.
The material in [29] was presented as follows. First of all, the authors considered features of organization of traditional single-chip system buses. After that they
described the composition of blocks of the suggested architecture of the universal
SoC bus. After that the authors presented a detailed description of the basic methods
underlying this security architecture of the SoC bus in the specific context of AMBA
bus. The end of [29] contains consideration of an interrupt handling method used
to obtain information about behavior of Trojans, which is designed to exclude the
possibility of influence of even embedded Trojans on the operation of the charged
computing system (device) by cutting off the critical connections between this system
bus and the charged IP block. Below we will present the main provisions of this
paper allowing the reader to understand the essence of this approach. If the readers
are deeply interested in the subject, they can further refer to the original paper [29].