7.1 Hardware and Software Methods …
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receive correct results of computations only with encrypted values. The obtained
result can be decrypted.
Implementation of such homomorphic functions is not a trivial task, and their
computation requires considerable expenses; at the same time, it is fairly difficult
to build a general purpose homomorphic encryption scheme. Like with data bus
scrambling, encryption and decryption units must be implemented in fully verified
hardware. Homomorphic encryption was not examined in [4]; instead, application of
the cryptographic algorithm with a public key (RSA encryption) was suggested and
analyzed. The use of the circuits implementing the Yao’s Garbled Circuit algorithm
[5] can be considered an alternative approach for obfuscation of data of computing
blocks.
It was also suggested in [4] to use the time protection method to prevent triggering
of a potentially introduced hardware Trojan within the confirmed state space. In
this case, the IC is checked for complete functional accuracy over a set number of
cycles. After performance of this set number of cycles, the microcircuit switches off
and back on, thus preventing the possibility of temporary activation of the Trojan.
Such hardware solution will help to preserve the context during these deactivations,
ensuring continuity of the computing process. The authors of the work here make a
quite logical assumption that any hardware Trojan that was at rest during complete
testing of the state space (in the space of states of time and inputs) will also be at rest
during the same period in operation conditions.
However, this option is not suitable for the triggers built with the help of the
elements of nonvolatile memory, accumulating mechanism (e.g., for charge accumulation on capacitance [6]), as well as externally (e.g., via a radio channel) controlled
triggers. The authors suggest bypassing the first one of these variants by visually
checking for presence of nonvolatile memory cells or special burning-out of such
cells during assembly of chips in package. Another solution consists in using the
technical process excluding implementation of non-volatile memory. Any hardware
used to restart the IC as well as means of maintaining context during the power off/on
period shall be verified.
From the literature, we also know about special gatekeepers that randomly alter the
order of events and introduce false events in the input sequences of various modules,
e.g., the memory controller, so that the saved or loaded sequences are disturbed. Such
safeguards ensure protection from activation of sequential Trojans.
The authors of [4] suggest using several versions of unreliable (unproven) functional IC blocks developed by various designers. Outputs from each module are
checked by comparing the obtained results to each other, and the true value is determined by voting. Obvious disadvantages of this method include high costs due to
the increased chip area and high energy consumption by the IC.
The authors of [7] suggest a protected architecture of system bus for the case of
system on chip (SoC). Its feature consists in the fact that this bus periodically changes
its stage from slave to master in order to detect the hardware Trojan that tries to block
it, using standard bus control commands in the process. Such activity is fairly easy
to detect using standard refreshable counters and simple heuristic algorithms, after
which the blacklist of such suspicious master/slave devices on the bus is formed
649
receive correct results of computations only with encrypted values. The obtained
result can be decrypted.
Implementation of such homomorphic functions is not a trivial task, and their
computation requires considerable expenses; at the same time, it is fairly difficult
to build a general purpose homomorphic encryption scheme. Like with data bus
scrambling, encryption and decryption units must be implemented in fully verified
hardware. Homomorphic encryption was not examined in [4]; instead, application of
the cryptographic algorithm with a public key (RSA encryption) was suggested and
analyzed. The use of the circuits implementing the Yao’s Garbled Circuit algorithm
[5] can be considered an alternative approach for obfuscation of data of computing
blocks.
It was also suggested in [4] to use the time protection method to prevent triggering
of a potentially introduced hardware Trojan within the confirmed state space. In
this case, the IC is checked for complete functional accuracy over a set number of
cycles. After performance of this set number of cycles, the microcircuit switches off
and back on, thus preventing the possibility of temporary activation of the Trojan.
Such hardware solution will help to preserve the context during these deactivations,
ensuring continuity of the computing process. The authors of the work here make a
quite logical assumption that any hardware Trojan that was at rest during complete
testing of the state space (in the space of states of time and inputs) will also be at rest
during the same period in operation conditions.
However, this option is not suitable for the triggers built with the help of the
elements of nonvolatile memory, accumulating mechanism (e.g., for charge accumulation on capacitance [6]), as well as externally (e.g., via a radio channel) controlled
triggers. The authors suggest bypassing the first one of these variants by visually
checking for presence of nonvolatile memory cells or special burning-out of such
cells during assembly of chips in package. Another solution consists in using the
technical process excluding implementation of non-volatile memory. Any hardware
used to restart the IC as well as means of maintaining context during the power off/on
period shall be verified.
From the literature, we also know about special gatekeepers that randomly alter the
order of events and introduce false events in the input sequences of various modules,
e.g., the memory controller, so that the saved or loaded sequences are disturbed. Such
safeguards ensure protection from activation of sequential Trojans.
The authors of [4] suggest using several versions of unreliable (unproven) functional IC blocks developed by various designers. Outputs from each module are
checked by comparing the obtained results to each other, and the true value is determined by voting. Obvious disadvantages of this method include high costs due to
the increased chip area and high energy consumption by the IC.
The authors of [7] suggest a protected architecture of system bus for the case of
system on chip (SoC). Its feature consists in the fact that this bus periodically changes
its stage from slave to master in order to detect the hardware Trojan that tries to block
it, using standard bus control commands in the process. Such activity is fairly easy
to detect using standard refreshable counters and simple heuristic algorithms, after
which the blacklist of such suspicious master/slave devices on the bus is formed