644
6 Reverse Engineering of Microcircuits
in the third layer of D-type triggers, final operations of the required function are
performed:
V5: f = Q
∗
¯
a ∧ b ∧ ¯
a ∧ ¯
b = a ∧ b ∨ ¯
a ∧ ¯
b;
V6: f = ¯
Q
∗
= ¯
a ∧ b ∧ a ∧ ¯
b = ¯
a ∧ b ∨ a ∧ ¯
b.
Such building of circuits is characterized by the fact that all logic gates of a single
layer of all triggers are switched at the same points in time relative to the common
LSIC clock signal.
In generalized form, the above rules of designing such protected ICs can be briefly
formulated as follows:
– Basic elements are the conjunctor, the inverter, and the non-symmetrical D-trigger
(Fig. 6.109);
– Chains between D-triggers during operation at a frequency can include sequences
of not more than (i + 1) gates;
– It is possible to expand functional possibilities of triggers by increasing the number
of D-inputs and distributing operations of logic functions over time layers of the
D-trigger (zero, first, second, and third) on condition of strict compliance with
the recommended points of connection of control information.
The above technical solutions were implemented in the reverse engineeringprotected microcircuits of the LSIC set for digital handling of signals, which is
designed to be used in control systems of phased antenna arrays (PAA).
References
1. V. Raja, K.J. Fernandes (eds.), Reverse Engineering, An Industrial Perspective (Springer-Verlag
London Limited)
2. Photonics.com, Using Reverse Engineering to Discover Patent Infringement, September 2010.
Julia Elvidge, Chipworks President
3. L. Radomskiy, Sixteen Years from the Adoption of the US Semiconductor Chip Protection
Act: Does the International Protection Work?
4. H. Nii, et al., A 45 nm High Performance Bulk Logic Platform Technology (CMOS6) Using
Ultra High NA (1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and
Porous Low-k BEOL. IEDM 2006 Technical Digest, pp. 685–688
5. R. Torrance, D. James, The State-of-the-Art in IC Reverse Engineering. Chipworks Inc. 3685
Richmond Road, Ottawa, Ontario, Canada K2H 5B7
6. ITRS, Metrology section
7. V. Vartanian, et al., Metrology challenges for 45 nm strained-Si devices, in 2005 International
Conference on Characterization and Metrology for ULSI Technology
8. D.A. James, Case Study: Looking Inside Apple’s iPOD Nano—A Teardown to
the Atomic Scale, http://electronics.wesrch.com/Paper/paper_details.php?id=EL1SE1KWR
X174&paper_type=pdf&type=%20author
9. K.-B. Cho, et al., A 1/2.5 inch 8 M pixel CMOS Image Sensor for Digital Cameras. ISSCC
Dig. Technical Papers, pp. 508–509 (2007)
6 Reverse Engineering of Microcircuits
in the third layer of D-type triggers, final operations of the required function are
performed:
V5: f = Q
∗
¯
a ∧ b ∧ ¯
a ∧ ¯
b = a ∧ b ∨ ¯
a ∧ ¯
b;
V6: f = ¯
Q
∗
= ¯
a ∧ b ∧ a ∧ ¯
b = ¯
a ∧ b ∨ a ∧ ¯
b.
Such building of circuits is characterized by the fact that all logic gates of a single
layer of all triggers are switched at the same points in time relative to the common
LSIC clock signal.
In generalized form, the above rules of designing such protected ICs can be briefly
formulated as follows:
– Basic elements are the conjunctor, the inverter, and the non-symmetrical D-trigger
(Fig. 6.109);
– Chains between D-triggers during operation at a frequency can include sequences
of not more than (i + 1) gates;
– It is possible to expand functional possibilities of triggers by increasing the number
of D-inputs and distributing operations of logic functions over time layers of the
D-trigger (zero, first, second, and third) on condition of strict compliance with
the recommended points of connection of control information.
The above technical solutions were implemented in the reverse engineeringprotected microcircuits of the LSIC set for digital handling of signals, which is
designed to be used in control systems of phased antenna arrays (PAA).
References
1. V. Raja, K.J. Fernandes (eds.), Reverse Engineering, An Industrial Perspective (Springer-Verlag
London Limited)
2. Photonics.com, Using Reverse Engineering to Discover Patent Infringement, September 2010.
Julia Elvidge, Chipworks President
3. L. Radomskiy, Sixteen Years from the Adoption of the US Semiconductor Chip Protection
Act: Does the International Protection Work?
4. H. Nii, et al., A 45 nm High Performance Bulk Logic Platform Technology (CMOS6) Using
Ultra High NA (1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and
Porous Low-k BEOL. IEDM 2006 Technical Digest, pp. 685–688
5. R. Torrance, D. James, The State-of-the-Art in IC Reverse Engineering. Chipworks Inc. 3685
Richmond Road, Ottawa, Ontario, Canada K2H 5B7
6. ITRS, Metrology section
7. V. Vartanian, et al., Metrology challenges for 45 nm strained-Si devices, in 2005 International
Conference on Characterization and Metrology for ULSI Technology
8. D.A. James, Case Study: Looking Inside Apple’s iPOD Nano—A Teardown to
the Atomic Scale, http://electronics.wesrch.com/Paper/paper_details.php?id=EL1SE1KWR
X174&paper_type=pdf&type=%20author
9. K.-B. Cho, et al., A 1/2.5 inch 8 M pixel CMOS Image Sensor for Digital Cameras. ISSCC
Dig. Technical Papers, pp. 508–509 (2007)