642
6 Reverse Engineering of Microcircuits
The second rule consists in the possibility of expanding the number of D-inputs
of the trigger as shown in Fig. 6.108d, where a trigger circuit with two D-inputs is
shown. As a result, the trigger output Q becomes the disjunction of D-inputs:
Q(t + 1) = D1(t) V D2(t).
The timing diagram of trigger operation in this case remains unchanged.
This rule makes it possible to easily design relatively complex circuits with a
minimum depth equal to one gate between D-triggers. In order to illustrate the application of this rule, Fig. 6.108e shows a trigger circuit implementing the function f =
aˆb V aˆb.
The third design rule expands functional possibilities of a nonsymmetric D-trigger,
but the term “tier” here is replaced with the term “time layer.” Figure 6.107d shows
division of the trigger into three time layers. The first layer includes logic gates V1,
V2, the second one—V2–V4, the third one—V5 and V6. The gates between separate
D-triggers of the LSIC belong to the zero time layer. In the first layer, output functions
of logic gates are linked to the input information D as follows:
q = D, q = −D;
in the second layer—and in the third layer—
1
All other information is master:
– at the inputs of layer I—feedbacks from the outputs of layer II: from V3 to the VI
input and from V4 to the V2 input;
– at the inputs of layer II—synchronization with V7 and information from V4 to
the V3 input;
– at the inputs of layer III—feedbacks from V5 to V6 and from V6 to V5.
In principle, it is possible to build any circuit according to the second and the
third rule only in the form of triggers with enhanced functionality. For this, logic
functions are distributed among time layers in strict compliance with the above
order of activation of control information and relations (Fig. 6.109); the function
implemented with the help of the trigger circuit (Fig. 6.108e) can be obtained using
the triggers with a wider logical functionality. Figure 6.109 shows the scheme of
generation of functions on triggers with expanded functional capabilities. Expansion
of capabilities consists in the fact that the triggers of variables a, b have additional
logic gates V4
and, subsequently, the outputs D-trigger with the function f is actually
absent—only its separate elements V3, V3
, V4, V4
, V5, V6, and V7 are required.
Logical operations of the function f are distributed among layers as follows:
V4
—in the second trigger layer, gates V3, V3
, V4, V4
perform the operations:
V3 : ¯
aV b; V3
: ¯
aV b; V4 : ¯
aV b; V4
: ¯
aV ¯
b;
6 Reverse Engineering of Microcircuits
The second rule consists in the possibility of expanding the number of D-inputs
of the trigger as shown in Fig. 6.108d, where a trigger circuit with two D-inputs is
shown. As a result, the trigger output Q becomes the disjunction of D-inputs:
Q(t + 1) = D1(t) V D2(t).
The timing diagram of trigger operation in this case remains unchanged.
This rule makes it possible to easily design relatively complex circuits with a
minimum depth equal to one gate between D-triggers. In order to illustrate the application of this rule, Fig. 6.108e shows a trigger circuit implementing the function f =
aˆb V aˆb.
The third design rule expands functional possibilities of a nonsymmetric D-trigger,
but the term “tier” here is replaced with the term “time layer.” Figure 6.107d shows
division of the trigger into three time layers. The first layer includes logic gates V1,
V2, the second one—V2–V4, the third one—V5 and V6. The gates between separate
D-triggers of the LSIC belong to the zero time layer. In the first layer, output functions
of logic gates are linked to the input information D as follows:
q = D, q = −D;
in the second layer—and in the third layer—
1
All other information is master:
– at the inputs of layer I—feedbacks from the outputs of layer II: from V3 to the VI
input and from V4 to the V2 input;
– at the inputs of layer II—synchronization with V7 and information from V4 to
the V3 input;
– at the inputs of layer III—feedbacks from V5 to V6 and from V6 to V5.
In principle, it is possible to build any circuit according to the second and the
third rule only in the form of triggers with enhanced functionality. For this, logic
functions are distributed among time layers in strict compliance with the above
order of activation of control information and relations (Fig. 6.109); the function
implemented with the help of the trigger circuit (Fig. 6.108e) can be obtained using
the triggers with a wider logical functionality. Figure 6.109 shows the scheme of
generation of functions on triggers with expanded functional capabilities. Expansion
of capabilities consists in the fact that the triggers of variables a, b have additional
logic gates V4
and, subsequently, the outputs D-trigger with the function f is actually
absent—only its separate elements V3, V3
, V4, V4
, V5, V6, and V7 are required.
Logical operations of the function f are distributed among layers as follows:
V4
—in the second trigger layer, gates V3, V3
, V4, V4
perform the operations:
V3 : ¯
aV b; V3
: ¯
aV b; V4 : ¯
aV b; V4
: ¯
aV ¯
b;