640
6 Reverse Engineering of Microcircuits
The most reliable and sufficiently quick standard IC trigger is the non-symmetrical
D-trigger, the scheme of which is shown in Fig. 6.107d.
Figure 6.107c shows timing diagrams of operation of real logic elements—inverter
and conjunction, which demonstrate that the inverter responds to the input information with a delay of t 3 . Taking this into account, it is easy to build a timing diagram
of operation of a basic D-trigger shown in Fig. 6.107f.
Analysis of the diagram in Fig. 6.107f shows that if the main trigger operates
for the same trigger, the clock frequency cannot exceed 1/6t 3 , while the time of the
cycle amounts to 6t 3 , where 3t 3 is the width of the pulse, and 3t is the duration of
the pause.
It is necessary to determine the limit possibilities of circuits including multiple
D-triggers operating in a serial chain to each other through a certain number of gates
(Fig. 6.108a).
In order to determine limit possibilities of trigger circuits with links through additional logic gates, let us present a brief analysis of operation of D-triggers depending
on the working frequency and the number of logic gates between the output Q and
the information input D. It can be performed using the timing diagram that takes into
account timing offset of the input information (at the D-input) and the spread of the
parameter t as shown in Fig. 6.108b.
If we denote the front edge of the synchronization pulse at the output of the valve
V7 as C+ and the front and rear edges of the information supplied to the D-input as
D+ and D
− , then it is easy to determine restrictions on the time offset of the input
information of the D-trigger relative to synchronization at the output of V7, namely:
1
Dn
+ −t+ >
2t
C D
; t + −t+ > 2
1
Dc
; t n − t+ >
21
cD
∗ ; t + −f+ > 2 1.
The diagram shown in Fig. 6.108c shows a detailed timing diagram of operation
of such trigger with all possible offsets of the input information at the limit frequency
of 1/6t, which is given in Fig. 6.108b. It allows for the following extremely important
conclusion: analysis of the state of information D at the V5, V6 outputs demonstrates
the possibility of stable operation of one
D-trigger for another one through a gate (see Fig. 6.107d) at the same limit
frequency of 1/6t, which is permissible for D-triggers operating for each other without
intermediate gates; only with inclusion of a sequence of two gates between D-triggers,
the limit frequency is reduced to 1/7t, etc.
This conclusion allows us to formulate the first rule for designing functional
diagrams of such protected ICs:
• For operation at the limit frequency of 1/6t and in circuits between D-triggers,
inclusion of not more than one logic gate in series is allowed;
• For operation at frequencies of 1/(6 + i)t, where i = 0, 1, 2, it is possible to
introduce not more than i + 1 gates between D-triggers of an LSIC (this is a
general rule).
6 Reverse Engineering of Microcircuits
The most reliable and sufficiently quick standard IC trigger is the non-symmetrical
D-trigger, the scheme of which is shown in Fig. 6.107d.
Figure 6.107c shows timing diagrams of operation of real logic elements—inverter
and conjunction, which demonstrate that the inverter responds to the input information with a delay of t 3 . Taking this into account, it is easy to build a timing diagram
of operation of a basic D-trigger shown in Fig. 6.107f.
Analysis of the diagram in Fig. 6.107f shows that if the main trigger operates
for the same trigger, the clock frequency cannot exceed 1/6t 3 , while the time of the
cycle amounts to 6t 3 , where 3t 3 is the width of the pulse, and 3t is the duration of
the pause.
It is necessary to determine the limit possibilities of circuits including multiple
D-triggers operating in a serial chain to each other through a certain number of gates
(Fig. 6.108a).
In order to determine limit possibilities of trigger circuits with links through additional logic gates, let us present a brief analysis of operation of D-triggers depending
on the working frequency and the number of logic gates between the output Q and
the information input D. It can be performed using the timing diagram that takes into
account timing offset of the input information (at the D-input) and the spread of the
parameter t as shown in Fig. 6.108b.
If we denote the front edge of the synchronization pulse at the output of the valve
V7 as C+ and the front and rear edges of the information supplied to the D-input as
D+ and D
− , then it is easy to determine restrictions on the time offset of the input
information of the D-trigger relative to synchronization at the output of V7, namely:
1
Dn
+ −t+ >
2t
C D
; t + −t+ > 2
1
Dc
; t n − t+ >
21
cD
∗ ; t + −f+ > 2 1.
The diagram shown in Fig. 6.108c shows a detailed timing diagram of operation
of such trigger with all possible offsets of the input information at the limit frequency
of 1/6t, which is given in Fig. 6.108b. It allows for the following extremely important
conclusion: analysis of the state of information D at the V5, V6 outputs demonstrates
the possibility of stable operation of one
D-trigger for another one through a gate (see Fig. 6.107d) at the same limit
frequency of 1/6t, which is permissible for D-triggers operating for each other without
intermediate gates; only with inclusion of a sequence of two gates between D-triggers,
the limit frequency is reduced to 1/7t, etc.
This conclusion allows us to formulate the first rule for designing functional
diagrams of such protected ICs:
• For operation at the limit frequency of 1/6t and in circuits between D-triggers,
inclusion of not more than one logic gate in series is allowed;
• For operation at frequencies of 1/(6 + i)t, where i = 0, 1, 2, it is possible to
introduce not more than i + 1 gates between D-triggers of an LSIC (this is a
general rule).