448
4 Hardware Trojans in Microcircuits
241. T. Yuan et al., A fully integrated CMOS transmitter for ultra-wideband applications, in
Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (IEEE Press, 2007),
pp. 39–42
242. H.G. Stratigopoulos, Y. Makris, Error moderation in low-cost machine-learning- based
analog/RF testing. IEEE Trans. Comput.-Aided Des. Integr.. Circ. Syst. 27(2), 339–351 (2008)
243. A. Candore, O. Kocabas, F. Koushanfar, Robust stable radiometric fingerprinting for frequency
reconfigurable devices, in Proceedings of the IEEE Int’l Workshop Hardware-Oriented
Security and Trust (IEEE CS Press, 2009), pp. 43–49
244. X. Wang, Hardware Trojan attacks: hardware Trojan attacks: threat analysis and low-cost
counter measures through golden-free detection and secure design (January 2014)
245. Y. Jin, Y. Makris, Hardware Trojans in Wireless Cryptographic ICs. IEEE Des. Test Comput.
27(1), 26–35 (2010)
246. I. Jin, Y. Makris, Hardware Trojan detection using path delay fingerprint. HOST (2008)
247. S. Narasimhan, X. Wang, D. Du, R.S. Chakraborty, S. Bhunia, TeSR: a robust temporal
self-referencing approach for hardware Trojan detection, in Proceedings of the 2011 IEEE
International Symposium on Hardware-Oriented Security and Trust (HOST 2011) (2011),
pp. 71–74, https://doi.org/10.1109/hst.2011.5954999
248. Cyber Security Awareness Week ESC, http://www.poly.edu/csaw-embedded
249. S.T. King et al., Designing and implementing malicious hardware, in USENIX. Workshop on
LEET (2008)
250. R.R. Rivest, The RC5 Encryption Algorithm. FSE (1994)
251. X. Wang, S. Narasimhan, A. Krishna, T. Mal-Sarkar, S. Bhunia, Sequential hardware
Trojans: side-channel aware design and placement, in IEEE 29th International Conference
on Computer Design (ICCD) (2011)
252. X. Wang, T. Mal-Sarkar, A. Krishna, S. Narasimhan, S. Bhunia, Software exploitable hardware Trojans in embedded processor, in IEEE. International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems (DFT) (2012)
253. X. Zhang et al., RON: an on-chip ring oscillator network for hardware Trojan detection, DATE
(2011)
254. I. Jin et al., Hardware Trojan detection using path delay fingerprint. HOST (2008)
255. J. Rajendran, V. Jyothi, O. Sinanoglu, R. Karri, Design and analysis of ring oscillator based
design-for-trust technique, in Proceedings of the 2011 IEEE 29th VLSI Test Symposium (VTS
2011) (2011), pp. 105–110. http://dx.doi.org/10.1109/VTS.2011.5783766
256. C. Lavin et al., Using hard macros to reduce FPGA compilation time, FPL (2010)
257. E.J. Marinissen et al., The role of test protocols in automated test generation for embeddedcore-based system ICs, J. Electr. Test.: Theory Appl. 18(4–5) (2002)
258. A. Maiti, J. Casarona, L. McHale, P. Schaumont, Large scale characterization of RO-PUF, in
Proceedings of the IEEE. International Workshop on Hardware-Oriented Security and Trust
(HOST) (2010)
259. K. Xiao, D. Forte, Y. Jin, R. Karri, S. Bhunia, M. Tehranipoor, Hardware Trojans: lessons
learned after one decade of research. ACM Trans. Des. Autom. Electron. Syst. 22(1). Article
6 (May 2016), 23 p., http://dx.doi.org/10.1145/2906147
260. M. Tehranipoor, C. Wang, Introduction to Hardware Security and Trust (Springer, 2002)
261. C Dunbar, G. Qu, Designing trusted embedded systems from finite state machines. ACM
Trans. Embedded Comput. Syst. 13, 5s, Article 153 (Oct. 2014), 20 p. http://dx.doi.org/10.
1145/2638555
262. Y. Shiyanovskii, F. Wolff, A. Rajendran, C. Papachristou, D. Weyer, W Clay, Process reliability based Trojans through NBTI and HCI effects, in Proceedings of the 2010 NASA/ESA
Conference on Adaptive Hardware and Systems (AHS 2010) (2010), pp. 215–222, http://dx.
doi.org/10.1109/AHS.2010.5546257
263. X. Zhang, K. Xiao, M. Tehranipoor, J. Rajendran, R. Karri, A study on the effectiveness
of Trojan detection techniques using a red team blue team approach, in Proceedings of the
2013 IEEE 31st VLSI Test Symposium (VTS 2013) (2013), pp. 1–3, https://doi.org/10.1109/
vts.2013.6548922
4 Hardware Trojans in Microcircuits
241. T. Yuan et al., A fully integrated CMOS transmitter for ultra-wideband applications, in
Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (IEEE Press, 2007),
pp. 39–42
242. H.G. Stratigopoulos, Y. Makris, Error moderation in low-cost machine-learning- based
analog/RF testing. IEEE Trans. Comput.-Aided Des. Integr.. Circ. Syst. 27(2), 339–351 (2008)
243. A. Candore, O. Kocabas, F. Koushanfar, Robust stable radiometric fingerprinting for frequency
reconfigurable devices, in Proceedings of the IEEE Int’l Workshop Hardware-Oriented
Security and Trust (IEEE CS Press, 2009), pp. 43–49
244. X. Wang, Hardware Trojan attacks: hardware Trojan attacks: threat analysis and low-cost
counter measures through golden-free detection and secure design (January 2014)
245. Y. Jin, Y. Makris, Hardware Trojans in Wireless Cryptographic ICs. IEEE Des. Test Comput.
27(1), 26–35 (2010)
246. I. Jin, Y. Makris, Hardware Trojan detection using path delay fingerprint. HOST (2008)
247. S. Narasimhan, X. Wang, D. Du, R.S. Chakraborty, S. Bhunia, TeSR: a robust temporal
self-referencing approach for hardware Trojan detection, in Proceedings of the 2011 IEEE
International Symposium on Hardware-Oriented Security and Trust (HOST 2011) (2011),
pp. 71–74, https://doi.org/10.1109/hst.2011.5954999
248. Cyber Security Awareness Week ESC, http://www.poly.edu/csaw-embedded
249. S.T. King et al., Designing and implementing malicious hardware, in USENIX. Workshop on
LEET (2008)
250. R.R. Rivest, The RC5 Encryption Algorithm. FSE (1994)
251. X. Wang, S. Narasimhan, A. Krishna, T. Mal-Sarkar, S. Bhunia, Sequential hardware
Trojans: side-channel aware design and placement, in IEEE 29th International Conference
on Computer Design (ICCD) (2011)
252. X. Wang, T. Mal-Sarkar, A. Krishna, S. Narasimhan, S. Bhunia, Software exploitable hardware Trojans in embedded processor, in IEEE. International Symposium on Defect and Fault
Tolerance in VLSI and Nanotechnology Systems (DFT) (2012)
253. X. Zhang et al., RON: an on-chip ring oscillator network for hardware Trojan detection, DATE
(2011)
254. I. Jin et al., Hardware Trojan detection using path delay fingerprint. HOST (2008)
255. J. Rajendran, V. Jyothi, O. Sinanoglu, R. Karri, Design and analysis of ring oscillator based
design-for-trust technique, in Proceedings of the 2011 IEEE 29th VLSI Test Symposium (VTS
2011) (2011), pp. 105–110. http://dx.doi.org/10.1109/VTS.2011.5783766
256. C. Lavin et al., Using hard macros to reduce FPGA compilation time, FPL (2010)
257. E.J. Marinissen et al., The role of test protocols in automated test generation for embeddedcore-based system ICs, J. Electr. Test.: Theory Appl. 18(4–5) (2002)
258. A. Maiti, J. Casarona, L. McHale, P. Schaumont, Large scale characterization of RO-PUF, in
Proceedings of the IEEE. International Workshop on Hardware-Oriented Security and Trust
(HOST) (2010)
259. K. Xiao, D. Forte, Y. Jin, R. Karri, S. Bhunia, M. Tehranipoor, Hardware Trojans: lessons
learned after one decade of research. ACM Trans. Des. Autom. Electron. Syst. 22(1). Article
6 (May 2016), 23 p., http://dx.doi.org/10.1145/2906147
260. M. Tehranipoor, C. Wang, Introduction to Hardware Security and Trust (Springer, 2002)
261. C Dunbar, G. Qu, Designing trusted embedded systems from finite state machines. ACM
Trans. Embedded Comput. Syst. 13, 5s, Article 153 (Oct. 2014), 20 p. http://dx.doi.org/10.
1145/2638555
262. Y. Shiyanovskii, F. Wolff, A. Rajendran, C. Papachristou, D. Weyer, W Clay, Process reliability based Trojans through NBTI and HCI effects, in Proceedings of the 2010 NASA/ESA
Conference on Adaptive Hardware and Systems (AHS 2010) (2010), pp. 215–222, http://dx.
doi.org/10.1109/AHS.2010.5546257
263. X. Zhang, K. Xiao, M. Tehranipoor, J. Rajendran, R. Karri, A study on the effectiveness
of Trojan detection techniques using a red team blue team approach, in Proceedings of the
2013 IEEE 31st VLSI Test Symposium (VTS 2013) (2013), pp. 1–3, https://doi.org/10.1109/
vts.2013.6548922