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95. C. Clavier, J.-S. Coron, N. Dabbous, Differential power analysis in the presence of hardware
countermeasures, in Cryptographic Hardware and Embedded Systems, vol. 1965, ser. Lecture
Notes in Computer Science (Springer, Berlin, Germany, 2000), pp. 252–263
96. P.C. Kocher, Leak-resistant cryptographic indexed key update, U.S. Patent 6 539 092 (2003)
97. J. Demme, R. Martin, A. Waksman, S. Sethumadhavan, Side-channel vulnerability factor:
a metric for measuring information leakage, in Proceedings of the IEEE International
Symposium on Computer Architecture (2012), pp. 106–117
98. J. Katz and V. Vaikuntanathan. Signature schemes with bounded leakage resilience, in
Advances in Cryptology, vol. 5912, ser. Lecture Notes in Computer Science (Springer, Berlin,
Germany, 2009), pp. 703–720
99. Y. Yu, F-X. Standaert, O. Pereira, M. Yung, Practical leakage-resilient pseudorandom generators, in Proceedings of the ACM Conference on Computer and Communications (2010),
pp. 141–151
100. F.-X. Standaert, O. Pereira, Y Yu, J.-J. Quisquater, M. Yung, E. Oswald, Leakage resilient
cryptography in practice, in Towards Hardware-Intrinsic Security, ser. Information Security
and Cryptography (Springer, Berlin, Germany, 2010), pp. 99–134
101. B. Yang, K. Wu, R. Karri, Secure scan: a design-for-test architecture for crypto chips, IEEE
Trans. Comput.-Aided Des. Integr. Circ. Syst. 25(10), 2287–2293 (2006)
102. D. Boneh, Cryptography I (2013), https://class.coursera.org/crypto-007/class/index
103. L. Domnitser, N. Abu-Ghazaleh, D. Ponomarev, A predictive model for cache-based side
channels in multicore and multithreaded microprocessors, in Computer Network Security, vol.
6258, ser. Lecture Notes in Computer Science (Springer, Berlin, Germany, 2010), pp. 70–85
104. J.-S. Coron, P Kocher, D. Naccache, Statistics and secret leakage, in Financial Cryptography,
vol. 1962, ser. Lecture Notes in Computer Science (Springer, Berlin, Germany, 2001), pp. 157–
173
105. Y. Alkabani, F. Koushanfar, Active hardware metering for intellectual property protection and
security, in Proceedings of the USENIX Security Symposium (2007), pp. 291–306
106. V. Huard, M. Denais, C. Parthasarathy, NBTI degradation: from physical mechanisms to
modelling. Microelectron. Reliab. 46(1), 1–23 (2006)
107. K. Chatterjee and D. Das. Semiconductor manufacturers’ efforts to improve trust in the electronic part supply chain, IEEE Trans. Compon. Packag. Technol. 30(3), 547–549 (2007). S.
Wei, A. Nahapetian and M. Potkonjak. Quantitative intellectual property protection using
physical-level characterization, IEEE Trans. Inf. Forensics Secur. 8(11), 1722–1730 (2013)
108. K. Huang, J. Carulli and Y Makris. Parametric counterfeit IC detection via support vector
machines, in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (2012), pp. 7–12
109. X. Zhang, K. Xiao, M. Tehranipoor, Path-delay fingerprinting for identification of recovered
ICs, in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in
VLSI and Nanotechnology Systems (2012), pp. 13–18
110. S. Skorobogatov, C. Woods, Breakthrough silicon scanning discovers backdoor in military
chip. University of Cambridge, Computer Laboratory, Cambridge, UK sps32@ cam.ac.uk 2
Quo Vadis Labs, London, UK, chris@quovadislabs.com
111. M. Tehranipoor, F. Koushanfar, A survey of hardware Trojan taxonomy and detection. IEEE
Des. Test Comput. (2010)
112. JTAG Boundary scan. IEEE Std 1149.1-2001
113. JTAG Programming specification. IEEE 1532-2002
114. J. DaRolt, G. Di Natale, M.-L. Flottes, B. Rouzeyre, New security threats against chips
containing scan chain structures. HOST (2011), 110–115
115. P. Kocher, J. Jaffe, B. Jun, Differential Power Analysis. CRYPTO 1999, LNCS, vol. 1666
(Springer, 1999), pp. 388–397
116. Actel, ISP and STAPL, Application Note AC171, http://www.actel.com/documents/ISPSTA
PLAN.pdf
117. Actel ProASIC3/E Production FPGAs, Features and Advantages (2007), http://www.actel.
com/documents/PA3_E_Tech_WP