310
4 Hardware Trojans in Microcircuits
[110] used such approach for extraction of both Passkey and the embedded defect
key, examining all possible changes from the signal sensor for correct and incorrect
calculations. For the classic DPA setting, in order to get at least 0.1 mV of differences,
at least 32 consecutive key bits must be selected on waveforms. Considering the input
noise of the probe with oscilloscope of 1 MW, it is necessary to execute at least 64
synchronous or 1024 asynchronous mean values. It takes 15 s to average the signal
on the MSO8104A for a positive SNR. Apparently, finding all unknown bits of the
key with DPA will take 232 times longer or about 2000 years. Further studies of
key operations of the embedded defects demonstrated that such operations unlock
many undocumented features, including reprogramming of protected memory and
IP access areas.
Another interesting result from [110] should be cited. The authors once again
returned to the JTAG registers that were not updated, as well as FROW, to check
if the attacker was able to change their values. After the authors of [110] unlocked
elements of the defects deliberately embedded by the authors, many registers immediately became unstable, and FROW was reprogrammed by the authors of [110] like
any standard flash memory, even though Actel claims that configuration files cannot
be reverse engineered with the help of JTAG or another method in ProASIC3 microcircuits and their latest generation of Flash FPGAs [118]. In other words, microcircuit
manufacturers state that their products are absolutely reliable, and access to reverse
engineering is therefore impossible. Nevertheless, the authors of [110] discovered
that Actel actually failed to implement sufficient protection from organization of
such access using a special activation key.
4.2.5 Hardware Trojans in Commercial Processors
4.2.5.1 Methods of Implementation of Hardware Trojans in Processors
Special services and relevant specialists of the leading industrial states addressed the
problems of hardware Trojans long before academic scientists, since the doctrines
of the relevant ministries and departments of such states had long considered this
scientific and technical direction as one of the forms of secret warfare between
special services in the field of high technologies. It is obvious that the results of
the corresponding studies and experimental studies are still stored in the reports
inaccessible to a wide audience.
One of the first openly published works dedicated to this problem [125] suggested
two most general approaches to creation of a malicious processor. The authors
demonstrate how electrical circuits of hardware Trojans can be embedded into the
processor to implement such private attack with the purpose of stealing passwords,
expanding access privileges, and providing automatic logging into the system. This
work is valuable due to the fact that it examines a general approach to support
a wide range of attacks with the possibility of their dynamical update. The work
demonstrates implementation of two modifications into the central processor or an
4 Hardware Trojans in Microcircuits
[110] used such approach for extraction of both Passkey and the embedded defect
key, examining all possible changes from the signal sensor for correct and incorrect
calculations. For the classic DPA setting, in order to get at least 0.1 mV of differences,
at least 32 consecutive key bits must be selected on waveforms. Considering the input
noise of the probe with oscilloscope of 1 MW, it is necessary to execute at least 64
synchronous or 1024 asynchronous mean values. It takes 15 s to average the signal
on the MSO8104A for a positive SNR. Apparently, finding all unknown bits of the
key with DPA will take 232 times longer or about 2000 years. Further studies of
key operations of the embedded defects demonstrated that such operations unlock
many undocumented features, including reprogramming of protected memory and
IP access areas.
Another interesting result from [110] should be cited. The authors once again
returned to the JTAG registers that were not updated, as well as FROW, to check
if the attacker was able to change their values. After the authors of [110] unlocked
elements of the defects deliberately embedded by the authors, many registers immediately became unstable, and FROW was reprogrammed by the authors of [110] like
any standard flash memory, even though Actel claims that configuration files cannot
be reverse engineered with the help of JTAG or another method in ProASIC3 microcircuits and their latest generation of Flash FPGAs [118]. In other words, microcircuit
manufacturers state that their products are absolutely reliable, and access to reverse
engineering is therefore impossible. Nevertheless, the authors of [110] discovered
that Actel actually failed to implement sufficient protection from organization of
such access using a special activation key.
4.2.5 Hardware Trojans in Commercial Processors
4.2.5.1 Methods of Implementation of Hardware Trojans in Processors
Special services and relevant specialists of the leading industrial states addressed the
problems of hardware Trojans long before academic scientists, since the doctrines
of the relevant ministries and departments of such states had long considered this
scientific and technical direction as one of the forms of secret warfare between
special services in the field of high technologies. It is obvious that the results of
the corresponding studies and experimental studies are still stored in the reports
inaccessible to a wide audience.
One of the first openly published works dedicated to this problem [125] suggested
two most general approaches to creation of a malicious processor. The authors
demonstrate how electrical circuits of hardware Trojans can be embedded into the
processor to implement such private attack with the purpose of stealing passwords,
expanding access privileges, and providing automatic logging into the system. This
work is valuable due to the fact that it examines a general approach to support
a wide range of attacks with the possibility of their dynamical update. The work
demonstrates implementation of two modifications into the central processor or an