2 The Smart “Things” in IoT
77
0
0
0
1
1
0
0
1
Rx
Receiver
Tx
Transmitter
Tx
Rx
Fig. 2.18 Configuration of universal asynchronous receiver/transmitter with one transmitter and
one receiver
Start
bit
5-9 data bit
Parity
bit
1-2 stop bits
Data frame
Packet
Fig. 2.19 The structure of UART packets
Although there is not any explicit external clock signal between two devices in
UART, both the transmitter and receiver contain their own internal clock. However,
this clock is not transmitted between devices. Instead, the internal clock of the
transmitter regulates how fast logic levels are created on the Tx side, and the internal
clock of the receiver regulates the sampling frequency on the Rx side. If the receiver
and transmitter are designed to receive or send data on different transmission
frequencies, UART communication will not work. In addition, their internal clock
signals have to be accurate in relationship to the target data-transmission frequency
and adequately stable in the presence of temperature variations over time.
UART data is arranged into packets for transmission. As shown in Fig. 2.19,
every packet includes 1 starting bit, 5–9 bits for data, an optional parity bit, and 1–2
stop bits [11]:
• Start Bit – Initial bit of each packet. This bit shows that the state of the data
line is changing from idle state to active state. Since typically the idle state is
represented by active high, the start bit is active low. Although a start bit is
mandatory in UART to be able to start the data-transmission process, it does
not actually transfer useful data; therefore, it is an overhead bit.
• Stop Bit – Final bit of each packet. This bit is logic high and similar to start bit
can be considered as an overhead bit.
77
0
0
0
1
1
0
0
1
Rx
Receiver
Tx
Transmitter
Tx
Rx
Fig. 2.18 Configuration of universal asynchronous receiver/transmitter with one transmitter and
one receiver
Start
bit
5-9 data bit
Parity
bit
1-2 stop bits
Data frame
Packet
Fig. 2.19 The structure of UART packets
Although there is not any explicit external clock signal between two devices in
UART, both the transmitter and receiver contain their own internal clock. However,
this clock is not transmitted between devices. Instead, the internal clock of the
transmitter regulates how fast logic levels are created on the Tx side, and the internal
clock of the receiver regulates the sampling frequency on the Rx side. If the receiver
and transmitter are designed to receive or send data on different transmission
frequencies, UART communication will not work. In addition, their internal clock
signals have to be accurate in relationship to the target data-transmission frequency
and adequately stable in the presence of temperature variations over time.
UART data is arranged into packets for transmission. As shown in Fig. 2.19,
every packet includes 1 starting bit, 5–9 bits for data, an optional parity bit, and 1–2
stop bits [11]:
• Start Bit – Initial bit of each packet. This bit shows that the state of the data
line is changing from idle state to active state. Since typically the idle state is
represented by active high, the start bit is active low. Although a start bit is
mandatory in UART to be able to start the data-transmission process, it does
not actually transfer useful data; therefore, it is an overhead bit.
• Stop Bit – Final bit of each packet. This bit is logic high and similar to start bit
can be considered as an overhead bit.