2 The Smart “Things” in IoT
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Interrupt Controller
Wake-up Controller
Memory Protection
Unit
Floating Point Unit
DSP
Debug System
Data Watchpoint
Breakpoint Unit
ITM Trace
ETM Trace
AMBA High-performance Bus (AHB)
ARM CORTEX-M Core
Memory
Peripherals
Input/Output
Clock & Reset
Simplified block diagram of Cortex Core
Simplified block diagram of a MCU built around
Cortex Core
CPU
Interrupt Controller
(NVIC)
Decoder
ALU
Interface
Register Bank
Instruction Fetch
Debug
System
Bus
Developed by ARM
Usually developed by
Chip manufacturers
Fig. 2.12 A simplified model of an ARM Cortex core and an ARM microcontroller
extra components (e.g., memory, peripherals, etc.) to the chip. Therefore, CortexM3-based microcontrollers from different manufacturers (or even from the same
manufacturer) can have different specifications and features such as memory sizes,
peripherals, etc.
Access Modes in Cortex-M3 It utilizes two access levels/modes (usually
user/normal level and privileged level). In the privileged level, applications can
access all memory (unless restricted by settings) and can utilize all instructions. The
reliability of the system can be increased by the separation of user and privileged
levels because configuration registers cannot be accessed or altered by suspicious
codes.
Pipeline in Cortex-M3 The ARM architecture is built on pipelining concept,
an architecture that allows several instructions to overlap during execution. Each
pipeline consists of several different stages that are responsible for executing a piece
of instruction in parallel. Each stage is connected to the next stage, forming a pipe
structure where instructions enter one end, work through each stage, and then exit
the other end. Pipelining increases the instruction throughput, which is computed by
the frequency with which instructions leave the pipeline. Simple ARM cores execute
instructions in three different stages (see Fig. 2.13):
• Fetch – Fetches the instruction from memory and brings to pipeline
• Decode – Decodes the instruction
• Execute – Executes the instruction (uses arithmetic and logic unit (ALU)) and
writes the result in appropriate registers
71
Interrupt Controller
Wake-up Controller
Memory Protection
Unit
Floating Point Unit
DSP
Debug System
Data Watchpoint
Breakpoint Unit
ITM Trace
ETM Trace
AMBA High-performance Bus (AHB)
ARM CORTEX-M Core
Memory
Peripherals
Input/Output
Clock & Reset
Simplified block diagram of Cortex Core
Simplified block diagram of a MCU built around
Cortex Core
CPU
Interrupt Controller
(NVIC)
Decoder
ALU
Interface
Register Bank
Instruction Fetch
Debug
System
Bus
Developed by ARM
Usually developed by
Chip manufacturers
Fig. 2.12 A simplified model of an ARM Cortex core and an ARM microcontroller
extra components (e.g., memory, peripherals, etc.) to the chip. Therefore, CortexM3-based microcontrollers from different manufacturers (or even from the same
manufacturer) can have different specifications and features such as memory sizes,
peripherals, etc.
Access Modes in Cortex-M3 It utilizes two access levels/modes (usually
user/normal level and privileged level). In the privileged level, applications can
access all memory (unless restricted by settings) and can utilize all instructions. The
reliability of the system can be increased by the separation of user and privileged
levels because configuration registers cannot be accessed or altered by suspicious
codes.
Pipeline in Cortex-M3 The ARM architecture is built on pipelining concept,
an architecture that allows several instructions to overlap during execution. Each
pipeline consists of several different stages that are responsible for executing a piece
of instruction in parallel. Each stage is connected to the next stage, forming a pipe
structure where instructions enter one end, work through each stage, and then exit
the other end. Pipelining increases the instruction throughput, which is computed by
the frequency with which instructions leave the pipeline. Simple ARM cores execute
instructions in three different stages (see Fig. 2.13):
• Fetch – Fetches the instruction from memory and brings to pipeline
• Decode – Decodes the instruction
• Execute – Executes the instruction (uses arithmetic and logic unit (ALU)) and
writes the result in appropriate registers