2 The Smart “Things” in IoT
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the peripheral devices. The microcontroller architecture is designed after a model
proposed by John von Neumann (1903–1957), which consists of a central processor
to perform arithmetic and logic operations, a control unit, memory and mass
storage, and input and output. This model is sometimes referred to as the Princeton
Architecture. The von Neumann model employs the same physical memory for
both instruction and data. As the instruction fetch and data access cannot happen
simultaneously, two clock cycles may be necessary for executing an instruction.
Figure 2.9 demonstrates a general block diagram of the von Neumann model
machine. Data and instruction are stored in a unified memory and accessed through
the same memory bus. The proportions of data and instruction in the memory
may vary from one application to another. The von Neumann model was later
enhanced for modern processors by separating instruction and data using dedicated
memory units. This new model, which is referred to as Harvard architecture, enables
transmission of data and instruction to take place on separate buses simultaneously.
As a generally accepted practice, the Harvard architecture utilizes two distinct
memories or separate instruction and data cache units connected to a unified
memory in high-performance systems. Figure 2.9 illustrates the block diagram of
an example of Harvard architecture. The main advantages of adding a second bus to
the system include:
• Pipelining – Thanks to the dedicated bus for instruction, a second instruction can
be obtained from memory as the first instruction is being executed, leading to a
greater performance. We will discuss the details of the pipelining concept later
in this section.
• Wider Instructions – In the Harvard architecture, the size of instruction memory
words may be larger from the data word; therefore, more instructions may be
fetched to the processor that may lead to performance improvement for compute
intensive applications.
Instruction
Memory
Data
Memory
CPU
Data bus
Data bus
Address bus
Address bus
Instruction
Memory
Data
Memory
CPU
Data bus
Address bus
Memory
Harvard Architecture
Von-Neumann Architecture
Fig. 2.9 von Neumann and Harvard processor architectures
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the peripheral devices. The microcontroller architecture is designed after a model
proposed by John von Neumann (1903–1957), which consists of a central processor
to perform arithmetic and logic operations, a control unit, memory and mass
storage, and input and output. This model is sometimes referred to as the Princeton
Architecture. The von Neumann model employs the same physical memory for
both instruction and data. As the instruction fetch and data access cannot happen
simultaneously, two clock cycles may be necessary for executing an instruction.
Figure 2.9 demonstrates a general block diagram of the von Neumann model
machine. Data and instruction are stored in a unified memory and accessed through
the same memory bus. The proportions of data and instruction in the memory
may vary from one application to another. The von Neumann model was later
enhanced for modern processors by separating instruction and data using dedicated
memory units. This new model, which is referred to as Harvard architecture, enables
transmission of data and instruction to take place on separate buses simultaneously.
As a generally accepted practice, the Harvard architecture utilizes two distinct
memories or separate instruction and data cache units connected to a unified
memory in high-performance systems. Figure 2.9 illustrates the block diagram of
an example of Harvard architecture. The main advantages of adding a second bus to
the system include:
• Pipelining – Thanks to the dedicated bus for instruction, a second instruction can
be obtained from memory as the first instruction is being executed, leading to a
greater performance. We will discuss the details of the pipelining concept later
in this section.
• Wider Instructions – In the Harvard architecture, the size of instruction memory
words may be larger from the data word; therefore, more instructions may be
fetched to the processor that may lead to performance improvement for compute
intensive applications.
Instruction
Memory
Data
Memory
CPU
Data bus
Data bus
Address bus
Address bus
Instruction
Memory
Data
Memory
CPU
Data bus
Address bus
Memory
Harvard Architecture
Von-Neumann Architecture
Fig. 2.9 von Neumann and Harvard processor architectures