470
M. N. Bojnordi and P. Behnam
83. J. Qiu, J. Wang, S. Yao, K. Guo, B. Li, E. Zhou, J. Yu, T. Tang, N. Xu, S. Song, et al, Going
deeper with embedded FPGA platform for convolutional neural network, in In Proceedings of
the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
84. R. Balasubramonian, J. Chang, T. Manning, J.H. Manning, R. Murphy, R. Nair, S. Swanson,
Near-data processing: insights from a MICRO-46 workshop, in IEEE Micro, 2014
85. M. Alian, S. Min, H. Asgharimoghaddam, A. Dhar, D. Wang, T. Roewer, A. McPadden, O.
O’Halloran, D. Chen, J. Xiong, D. Kim, Application-transparent near-memory processing
architecture with memory channel network,“ in Annual IEEE/ACM International Symposium
on Microarchitecture (MICRO), 2018
86. A. Nag, R. Balasubramonian, V. Srikumar, R. Walker, A. Shafiee, J. Strachan, N. Muralimanohar, Newton: gravitating towards the physical limits of crossbar acceleration,” in IEEE
Micro, 2018
87. Q. Guo, X. Guo, R.I.E. Patel, E.G. Friedman, Ac-DIMM: associative computing with STTMRAM, in ACM SIGARCH Computer Architecture News, 2013
88. J. Su, J. Liu, D.B. Thomas, P.Y. Cheung, Neural network based reinforcement learning
acceleration on FPGA platforms, in ACM SIGARCH Computer Architecture News, 2017
89. Y. Zhu, Y.P.Y. Zhang, Large-scale restricted Boltzmann machines on single GPU, in IEEE
International Conference on Big Data, 2013
90. S. Li, D. Niu, K. Malladi, H. Zheng, B. Brennan, Y. Xie, Drisa: a dram-based reconfigurable
in-situ accelerator, in Proceedings of the 50th Annual IEEE/ACM International Symposium
on Microarchitecture, 2017
91. Q. Guo, X. Guo, Y. Bai, E. Ipek, A resistive TCAM accelerator for data-intensive computing,
in In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011
92. A. Pal Chowdhury, P. Kulkarni, M. Nazm Bojnordi, MB-CNN: memristive binary convolutional neural networks for embedded mobile devices. J. Low Power Electron. Appl. 8(38),
1–27 (2018)
93. Y. Karthik Rupesh, P. Behnam, G. Reddy Pandla, M. Miryala, M. Bojnordi, Accelerating
k-medians clustering using a novel 4t-4r RRAM cell, in IEEE Trans-actions on Very Large
Scale Integration (VLSI) Systems, 2018
94. Y. Li, S. Lee, K. Oowada, H. Nguyen, Q. Nguyen, N. Mokhlesi, C. Hsu, J. Li, V.
Ramachandra, T. Kamei, et al, 128Gb 3b/Cell NAND flash memory in 19nm technology
with 18MB/s write rate and 400Mb/s toggle mode, in In Proceedings of the 2012 IEEE
International on Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012
95. D. Takashima, Y. Nagadomi, T. Ozaki, A 100 MHz ladder FeRAM design with capacitancecoupled-bitline (CCB) cell, in IEEE J. Solid-State Circuits, 2011
96. R. Simpson, M. Krbal, P. Fons, A. Kolobov, J. Tominaga, T. Uruga, H. Tanida, Toward the
ultimate limit of phase change in Ge2Sb2Te5. Nano Lett. 10(2), 414–419 (2010)
97. A. Benoist, S. Blonkowski, S. Jeannot, S. Denorme, J. Damiens, J. Berger, P. Candelier, E.
Vianello, H. Grampeix, J. Nodin, et al, 28 nm advanced CMOS resistive RAM solution as
embedded non-volatile memory, in In Proceedings of the 2014 IEEE International Reliability
Physics Symposium, 2014
98. M. Ueki, K. Akeuchi, T. Yamamoto, A. Tanabe, N. Ikarashi, M. Saitoh, T. Nagumo, H.
Sunamura, M. Narihiro, K. Uejima, et al, Low-power embedded ReRAM technology for IoT
applications, in In Proceedings of the 2015 Symposium on VLSI Circuits (VLSI Circuits),
2015
99. M. Oskin, F.T. Chong, T. Sherwood, Active pages: a computation model for intelligent
memory, in in Proc. 25th Annu. Int. Symp. Comput. Archit., 1998
100. M. Qureshi, M. Franceschini, L. Lastras-Montaño, J. Karidis, Morphable memory system: a
robust architecture for exploiting multi-level phase change memories, in In ACM SIGARCH
Computer Architecture News, 2010
101. B. Razavi, Principles of Data Conversion System Design. (Wiley-IEEE Press, 1995)
102. W. Kester, I. Analog Devices, Data Conversion Handbook (Analog Devices, Norwood, MA,
2005)
M. N. Bojnordi and P. Behnam
83. J. Qiu, J. Wang, S. Yao, K. Guo, B. Li, E. Zhou, J. Yu, T. Tang, N. Xu, S. Song, et al, Going
deeper with embedded FPGA platform for convolutional neural network, in In Proceedings of
the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
84. R. Balasubramonian, J. Chang, T. Manning, J.H. Manning, R. Murphy, R. Nair, S. Swanson,
Near-data processing: insights from a MICRO-46 workshop, in IEEE Micro, 2014
85. M. Alian, S. Min, H. Asgharimoghaddam, A. Dhar, D. Wang, T. Roewer, A. McPadden, O.
O’Halloran, D. Chen, J. Xiong, D. Kim, Application-transparent near-memory processing
architecture with memory channel network,“ in Annual IEEE/ACM International Symposium
on Microarchitecture (MICRO), 2018
86. A. Nag, R. Balasubramonian, V. Srikumar, R. Walker, A. Shafiee, J. Strachan, N. Muralimanohar, Newton: gravitating towards the physical limits of crossbar acceleration,” in IEEE
Micro, 2018
87. Q. Guo, X. Guo, R.I.E. Patel, E.G. Friedman, Ac-DIMM: associative computing with STTMRAM, in ACM SIGARCH Computer Architecture News, 2013
88. J. Su, J. Liu, D.B. Thomas, P.Y. Cheung, Neural network based reinforcement learning
acceleration on FPGA platforms, in ACM SIGARCH Computer Architecture News, 2017
89. Y. Zhu, Y.P.Y. Zhang, Large-scale restricted Boltzmann machines on single GPU, in IEEE
International Conference on Big Data, 2013
90. S. Li, D. Niu, K. Malladi, H. Zheng, B. Brennan, Y. Xie, Drisa: a dram-based reconfigurable
in-situ accelerator, in Proceedings of the 50th Annual IEEE/ACM International Symposium
on Microarchitecture, 2017
91. Q. Guo, X. Guo, Y. Bai, E. Ipek, A resistive TCAM accelerator for data-intensive computing,
in In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011
92. A. Pal Chowdhury, P. Kulkarni, M. Nazm Bojnordi, MB-CNN: memristive binary convolutional neural networks for embedded mobile devices. J. Low Power Electron. Appl. 8(38),
1–27 (2018)
93. Y. Karthik Rupesh, P. Behnam, G. Reddy Pandla, M. Miryala, M. Bojnordi, Accelerating
k-medians clustering using a novel 4t-4r RRAM cell, in IEEE Trans-actions on Very Large
Scale Integration (VLSI) Systems, 2018
94. Y. Li, S. Lee, K. Oowada, H. Nguyen, Q. Nguyen, N. Mokhlesi, C. Hsu, J. Li, V.
Ramachandra, T. Kamei, et al, 128Gb 3b/Cell NAND flash memory in 19nm technology
with 18MB/s write rate and 400Mb/s toggle mode, in In Proceedings of the 2012 IEEE
International on Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012
95. D. Takashima, Y. Nagadomi, T. Ozaki, A 100 MHz ladder FeRAM design with capacitancecoupled-bitline (CCB) cell, in IEEE J. Solid-State Circuits, 2011
96. R. Simpson, M. Krbal, P. Fons, A. Kolobov, J. Tominaga, T. Uruga, H. Tanida, Toward the
ultimate limit of phase change in Ge2Sb2Te5. Nano Lett. 10(2), 414–419 (2010)
97. A. Benoist, S. Blonkowski, S. Jeannot, S. Denorme, J. Damiens, J. Berger, P. Candelier, E.
Vianello, H. Grampeix, J. Nodin, et al, 28 nm advanced CMOS resistive RAM solution as
embedded non-volatile memory, in In Proceedings of the 2014 IEEE International Reliability
Physics Symposium, 2014
98. M. Ueki, K. Akeuchi, T. Yamamoto, A. Tanabe, N. Ikarashi, M. Saitoh, T. Nagumo, H.
Sunamura, M. Narihiro, K. Uejima, et al, Low-power embedded ReRAM technology for IoT
applications, in In Proceedings of the 2015 Symposium on VLSI Circuits (VLSI Circuits),
2015
99. M. Oskin, F.T. Chong, T. Sherwood, Active pages: a computation model for intelligent
memory, in in Proc. 25th Annu. Int. Symp. Comput. Archit., 1998
100. M. Qureshi, M. Franceschini, L. Lastras-Montaño, J. Karidis, Morphable memory system: a
robust architecture for exploiting multi-level phase change memories, in In ACM SIGARCH
Computer Architecture News, 2010
101. B. Razavi, Principles of Data Conversion System Design. (Wiley-IEEE Press, 1995)
102. W. Kester, I. Analog Devices, Data Conversion Handbook (Analog Devices, Norwood, MA,
2005)