9 Emerging Hardware Technologies for IoT Data Processing
467
21. D.H. Woo, N.H. Seong, D.L. Lewis, H.-H.S. Lee, An optimized 3D-stacked memory
architecture by exploiting excessive, high-density TSV bandwidth, in 16th International
Symposium on High Performance Computer Architecture (HPCA), 2010
22. P. Mike, An Intro to MCDRAM (High Bandwidth Memory) on Knights Landing, Intel HPC
Developer Conference, 2016
23. J. Ahn, S. Yoo, O. Mutlu, K. Choi, PIM-enabled instructions: a low-overhead, locality-aware
processing-in-memory architecture, in ACM/IEEE 42nd Annual International Symposium on
Computer Architecture (ISCA), 2015
24. D. Kim, J. Kung, S. Chai, S. Yalamanchili, S. Mukhopadhyay, Neurocube: a programmable
digital neuromorphic architecture with high-density 3D memory, in ACM/IEEE 43rd Annual
International Symposium on Computer Architecture (ISCA), 2016
25. K. Hsieh, E. Ebrahimi, G. Kim, N. Chatterjee, M. O’Connor, N. Vijaykumar, O. Mutlu, S.W.
Keckler, Transparent offloading and mapping (TOM): enabling programmer-transparent neardata processing in GPU systems. ACM SIGARCH Comput. Archit. News 44(3) (2016)
26. M.N. Bojnordi, F. Nasrullah, ReTagger: an efficient controller for DRAM cache architectures,
in Design Automation Conference (DAC), Las Vegas, NV, 2019
27. F. Pan, S. Gao, C. Chen, C. Song, F. Zeng, Recent progress in resistive random access
memories: materials, switching mechanisms, and performance. Mater. Sci. Eng.: R: Rep. 83,
1–59 (2014)
28. C. Ho, C.-L. Hsu, C.-C. Chen, J.-T. Liu, C.-S. Wu, C.-C. Huang, C. Hu, F.-L. Yang, 9nm
half-pitch functional resistive memory cell with <1μa programming current using thermally
oxidized sub-stoichiometric wo x film, in in Electron Devices Meeting (IEDM), 2010
29. B. Govoreanu, G. Kar, Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini, I. Radu, L. Goux, S.
Clima, R. Degraeve et al., 10 × 10 nm 2 hf/hfo x crossbar resistive RAM with excellent
performance, in Electron Devices Meeting (IEDM), 2011
30. A.C. Torrezan, J.P. Strachan, G. Medeiros-Ribeiro, R.S. Williams, Sub-nanosecond switching
of a tantalum oxide memristor. Nanotechnology 22(48), 485203 (2011)
31. B.J. Choi, A.C. Torrezan, K.J. Norris, F. Miao, J.P. Strachan, M.-X. Zhang, D.A. Ohlberg, N.P.
Kobayashi, J.J. Yang, R.S. Williams, Electrical performance and scalability of pt dispersed
SiO 2 nanometallic resistance switch. Nano Lett. 13(7), 3213–3217 (2013)
32. S. Lai. Current status of the phase change memory and its future, in In Electron Devices
Meeting, 2003
33. C. Cheng, C. Tsai, A. Chin, F. Yeh, High performance ultra-low energy RRAM with good
retention and endurance, in In Electron Devices Meeting (IEDM), 2010
34. C. Cheng, A. Chin, F. Yeh, Novel ultra-low power RRAM with good endurance and retention,
in In VLSI Technology (VLSIT), 2010
35. H. Akinaga, H. Shima, Resistive random access memory (RERAM) based on metal oxides,
in Proceedings of the IEEE, 2010
36. S. Sheu, M. Chang, K. Lin, C. Wu, Y. Chen, P. Chiu, C. Kuo, Y. Yang, P. Chiang, W. Lin,
C. Lin, A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access
time and 160ns MLC-access capability, in IEEE International Solid-State Circuits Conference
Digest of Technical Papers (ISSCC), 2011
37. M. Zangeneh, A. Joshi, Design and optimization of nonvolatile multibit 1T1R resistive RAM,
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
38. J.J. Yang, M.D. Pickett, X. Li, D.A.A. Ohlberg, D.R. Stewart, R.S. Williams, Memristive
switching mechanism for metal/oxide/metal nanodevices. Nat. Nanotechnol. 3, 429–433
(2008)
39. D. Niu, C. Xu, N. Muralimanohar, N. Jouppi, Y. Xie, Design trade-offs for high density crosspoint resistive memory, in ACM/IEEE International Symposium on Low Power Electronics
and Design, 2012
40. C. Xu, X. Dong, N. Jouppi, Y. Xie, Design implications of memristor-based RRAM crosspoint structures, in In Proceedings of the Design, Automation & Test in Europe Conference &
Exhibition (DATE), 2011
467
21. D.H. Woo, N.H. Seong, D.L. Lewis, H.-H.S. Lee, An optimized 3D-stacked memory
architecture by exploiting excessive, high-density TSV bandwidth, in 16th International
Symposium on High Performance Computer Architecture (HPCA), 2010
22. P. Mike, An Intro to MCDRAM (High Bandwidth Memory) on Knights Landing, Intel HPC
Developer Conference, 2016
23. J. Ahn, S. Yoo, O. Mutlu, K. Choi, PIM-enabled instructions: a low-overhead, locality-aware
processing-in-memory architecture, in ACM/IEEE 42nd Annual International Symposium on
Computer Architecture (ISCA), 2015
24. D. Kim, J. Kung, S. Chai, S. Yalamanchili, S. Mukhopadhyay, Neurocube: a programmable
digital neuromorphic architecture with high-density 3D memory, in ACM/IEEE 43rd Annual
International Symposium on Computer Architecture (ISCA), 2016
25. K. Hsieh, E. Ebrahimi, G. Kim, N. Chatterjee, M. O’Connor, N. Vijaykumar, O. Mutlu, S.W.
Keckler, Transparent offloading and mapping (TOM): enabling programmer-transparent neardata processing in GPU systems. ACM SIGARCH Comput. Archit. News 44(3) (2016)
26. M.N. Bojnordi, F. Nasrullah, ReTagger: an efficient controller for DRAM cache architectures,
in Design Automation Conference (DAC), Las Vegas, NV, 2019
27. F. Pan, S. Gao, C. Chen, C. Song, F. Zeng, Recent progress in resistive random access
memories: materials, switching mechanisms, and performance. Mater. Sci. Eng.: R: Rep. 83,
1–59 (2014)
28. C. Ho, C.-L. Hsu, C.-C. Chen, J.-T. Liu, C.-S. Wu, C.-C. Huang, C. Hu, F.-L. Yang, 9nm
half-pitch functional resistive memory cell with <1μa programming current using thermally
oxidized sub-stoichiometric wo x film, in in Electron Devices Meeting (IEDM), 2010
29. B. Govoreanu, G. Kar, Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini, I. Radu, L. Goux, S.
Clima, R. Degraeve et al., 10 × 10 nm 2 hf/hfo x crossbar resistive RAM with excellent
performance, in Electron Devices Meeting (IEDM), 2011
30. A.C. Torrezan, J.P. Strachan, G. Medeiros-Ribeiro, R.S. Williams, Sub-nanosecond switching
of a tantalum oxide memristor. Nanotechnology 22(48), 485203 (2011)
31. B.J. Choi, A.C. Torrezan, K.J. Norris, F. Miao, J.P. Strachan, M.-X. Zhang, D.A. Ohlberg, N.P.
Kobayashi, J.J. Yang, R.S. Williams, Electrical performance and scalability of pt dispersed
SiO 2 nanometallic resistance switch. Nano Lett. 13(7), 3213–3217 (2013)
32. S. Lai. Current status of the phase change memory and its future, in In Electron Devices
Meeting, 2003
33. C. Cheng, C. Tsai, A. Chin, F. Yeh, High performance ultra-low energy RRAM with good
retention and endurance, in In Electron Devices Meeting (IEDM), 2010
34. C. Cheng, A. Chin, F. Yeh, Novel ultra-low power RRAM with good endurance and retention,
in In VLSI Technology (VLSIT), 2010
35. H. Akinaga, H. Shima, Resistive random access memory (RERAM) based on metal oxides,
in Proceedings of the IEEE, 2010
36. S. Sheu, M. Chang, K. Lin, C. Wu, Y. Chen, P. Chiu, C. Kuo, Y. Yang, P. Chiang, W. Lin,
C. Lin, A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access
time and 160ns MLC-access capability, in IEEE International Solid-State Circuits Conference
Digest of Technical Papers (ISSCC), 2011
37. M. Zangeneh, A. Joshi, Design and optimization of nonvolatile multibit 1T1R resistive RAM,
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
38. J.J. Yang, M.D. Pickett, X. Li, D.A.A. Ohlberg, D.R. Stewart, R.S. Williams, Memristive
switching mechanism for metal/oxide/metal nanodevices. Nat. Nanotechnol. 3, 429–433
(2008)
39. D. Niu, C. Xu, N. Muralimanohar, N. Jouppi, Y. Xie, Design trade-offs for high density crosspoint resistive memory, in ACM/IEEE International Symposium on Low Power Electronics
and Design, 2012
40. C. Xu, X. Dong, N. Jouppi, Y. Xie, Design implications of memristor-based RRAM crosspoint structures, in In Proceedings of the Design, Automation & Test in Europe Conference &
Exhibition (DATE), 2011