7 Intelligent and Connected Cyber-Physical Systems: A Perspective. . .
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requirements on control performances and physical constraints, control algorithms,
and stability guarantee. The cross-layer interplay between the cyber and physical
components will be discussed with memory-aware CPS design as an example.
7.2.1 Cyber Components
In the CPS architecture, there is often a hierarchy of memory resources, such as the
flash memory and the on-chip memory in Fig. 7.1. As discussed in the introduction,
cache reuse depends on the execution order of applications. Given a collection of
applications (e.g., C 1 , C 2 , C 3 ) sharing the same processor and memory resources,
it is conventional to run them in a round-robin fashion (C 1 , C 2 , C 3 , C 1 , C 2 , C 3 ,
· · · ). Since the code for different applications is usually different, the on-chip
cache is frequently refreshed in this process. This results in poor cache reuse and
long WCET. In order to address this issue, each application can be consecutively
executed multiple times, which will increase the cache reuse and shorten the WCET.
An example execution order (C 1 (1), C 1 (2), C 1 (3), C 2 (1), C 2 (2), C 2 (3), C 3 (1),
C 3 (2), C 3 (3), · · · ) is illustrated in Fig. 7.2, where C i (j) denotes the jth execution of
the application C i . Before the first execution C i (1), the cache is either empty (i.e.,
cold cache) or filled with instructions from other applications, which are not used
by C i (equivalent to cold cache). The WCET of C i (1) can be computed by a number
of existing standard techniques. Before the second execution C i (2), the instructions
in the cache are from the same application C i and thus can be reused. This results
in more cache hits and hence shorter WCET. Depending on which execution path
the program takes, the amount of WCET reduction varies. Therefore, a technique is
required to compute the guaranteed WCET reduction of C i (2) and C i (3) relative to
C i (1), independent of the path taken.
Fig. 7.2 An example memory-aware execution order with three applications
361
requirements on control performances and physical constraints, control algorithms,
and stability guarantee. The cross-layer interplay between the cyber and physical
components will be discussed with memory-aware CPS design as an example.
7.2.1 Cyber Components
In the CPS architecture, there is often a hierarchy of memory resources, such as the
flash memory and the on-chip memory in Fig. 7.1. As discussed in the introduction,
cache reuse depends on the execution order of applications. Given a collection of
applications (e.g., C 1 , C 2 , C 3 ) sharing the same processor and memory resources,
it is conventional to run them in a round-robin fashion (C 1 , C 2 , C 3 , C 1 , C 2 , C 3 ,
· · · ). Since the code for different applications is usually different, the on-chip
cache is frequently refreshed in this process. This results in poor cache reuse and
long WCET. In order to address this issue, each application can be consecutively
executed multiple times, which will increase the cache reuse and shorten the WCET.
An example execution order (C 1 (1), C 1 (2), C 1 (3), C 2 (1), C 2 (2), C 2 (3), C 3 (1),
C 3 (2), C 3 (3), · · · ) is illustrated in Fig. 7.2, where C i (j) denotes the jth execution of
the application C i . Before the first execution C i (1), the cache is either empty (i.e.,
cold cache) or filled with instructions from other applications, which are not used
by C i (equivalent to cold cache). The WCET of C i (1) can be computed by a number
of existing standard techniques. Before the second execution C i (2), the instructions
in the cache are from the same application C i and thus can be reused. This results
in more cache hits and hence shorter WCET. Depending on which execution path
the program takes, the amount of WCET reduction varies. Therefore, a technique is
required to compute the guaranteed WCET reduction of C i (2) and C i (3) relative to
C i (1), independent of the path taken.
Fig. 7.2 An example memory-aware execution order with three applications