1 Self-explaining Digital Systems
19
References
1. Basu, P., Das, S., Banerjee, A., Dasgupta, P., Chakrabarti, P., Mohan, C., Fix, L., Armoni, R.:
Design-intent coverage: a new paradigm for formal property verification. IEEE Trans. CAD
25(10), 1922–1934 (2006)
2. Bormann, J.: Complete Functional Verification. Ph.D. Thesis, University of Kaiserslautern
(2009). English translation 2017
3. Chan, W.: Temporal-logic queries. In: Computer Aided Verification. Lecture Notes in Computer Science, vol. 1855, pp. 450–463 (2000)
4. Clarke, E., Grumberg, O., Long, D.: Model checking and abstraction. In: Symposium on
Principles of Programming Languages, pp. 342–354 (1992)
5. Clarke, E.M., Grumberg, O., Peled, D.: Model Checking. MIT Press, Cambridge, MA (2001)
6. Deutsch, S., Chakrabarty, K.: Massive signal tracing using on-chip dram for in-system silicon
debug. In: 2014 International Test Conference, pp. 1–10. IEEE, Piscataway (2014). https://doi.
org/10.1109/TEST.2014.7035363
7. Drechsler, R., Lüth, C., Fey, G., Güneysu, T.: Towards self-explaining digital systems: a design
methodology for the next generation. In: International Verification and Security Workshop
(IVSW), pp. 1–6. IEEE, Piscataway (2018)
8. Fähndrich, J., Ahrndt, S., Albayrak, S.: Towards self-explaining agents. In: Trends in Practical
Applications of Agents and Multiagent Systems, pp. 147–154. Springer, Berlin (2013)
9. Fähndrich, J., Ahrndt, S., Albayrak, S.: Self-explanation through semantic annotation: a survey.
In: Position Papers of the 2015 Federated Conference on Computer Science and Information
Systems (FedCSIS) (2015)
10. Fey, G., Drechsler, R.: Self-explaining digital systems—some technical steps. In:
ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (2019)
11. Fey, G., Staber, S., Bloem, R., Drechsler, R.: Automatic fault localization for property
checking. IEEE Trans. CAD 27(6), 1138–1149 (2008)
12. Fraud, R., Clrot, F.: A methodology to explain neural network classification. Neural Netw.
15(2), 237–246 (2002). https://doi.org/10.1016/S0893-6080(01)00127-7
13. Goldberg, E., Novikov, Y.: Verification of proofs of unsatisfiability for CNF formulas. In:
Design, Automation and Test in Europe, pp. 886–891. IEEE Computer Society, Washington,
DC (2003)
14. Große, D., Kühne, U., Drechsler, R.: Analyzing functional coverage in bounded model
checking. IEEE Trans. CAD 27(7), 1305–1314 (2008)
15. Keng, B., Veneris, A.: Scaling VLSI design debugging with interpolation. In: International
Conference on Formal Methods in CAD, pp. 144–151. IEEE, Piscataway (2009). https://doi.
org/10.1109/FMCAD.2009.5351130
16. Kephart, J.O., Chess, D.M.: The vision of autonomic computing. Computer 36(1), 41–50
(2003)
17. Korel, B., Laski, J.: Dynamic program slicing. Inf. Process. Lett. 29(3), 155–163 (1988).
https://doi.org/10.1016/0020-0190(88)90054-3
18. Lamport, L.: Time, clocks, and the ordering of events in a distributed system. Commun. ACM
21(7), 558–565 (1978). https://doi.org/10.1145/359545.359563
19. Lewis, D.: Causation. J. Philos. 70(17), 556–567 (1973)
20. Liffiton, M., Sakallah, K.: Algorithms for computing minimal unsatisfiable subsets of constraints. J. Autom. Reason. 40(1), 1–33 (2007)
21. Lin, D., Singh, E., Barrett, C., Mitra, S.: A structured approach to post-silicon validation and
debug using symbolic quick error detection. In: 2015 IEEE International Test Conference
(ITC), pp. 1–10. IEEE, Piscataway (2015). https://doi.org/10.1109/TEST.2015.7342397
22. Liu, W.: Real-time fault-tolerant control systems. In: Leondes, C.T. (ed.) Expert Systems,
pp. 267–304. Academic, London (2002)
19
References
1. Basu, P., Das, S., Banerjee, A., Dasgupta, P., Chakrabarti, P., Mohan, C., Fix, L., Armoni, R.:
Design-intent coverage: a new paradigm for formal property verification. IEEE Trans. CAD
25(10), 1922–1934 (2006)
2. Bormann, J.: Complete Functional Verification. Ph.D. Thesis, University of Kaiserslautern
(2009). English translation 2017
3. Chan, W.: Temporal-logic queries. In: Computer Aided Verification. Lecture Notes in Computer Science, vol. 1855, pp. 450–463 (2000)
4. Clarke, E., Grumberg, O., Long, D.: Model checking and abstraction. In: Symposium on
Principles of Programming Languages, pp. 342–354 (1992)
5. Clarke, E.M., Grumberg, O., Peled, D.: Model Checking. MIT Press, Cambridge, MA (2001)
6. Deutsch, S., Chakrabarty, K.: Massive signal tracing using on-chip dram for in-system silicon
debug. In: 2014 International Test Conference, pp. 1–10. IEEE, Piscataway (2014). https://doi.
org/10.1109/TEST.2014.7035363
7. Drechsler, R., Lüth, C., Fey, G., Güneysu, T.: Towards self-explaining digital systems: a design
methodology for the next generation. In: International Verification and Security Workshop
(IVSW), pp. 1–6. IEEE, Piscataway (2018)
8. Fähndrich, J., Ahrndt, S., Albayrak, S.: Towards self-explaining agents. In: Trends in Practical
Applications of Agents and Multiagent Systems, pp. 147–154. Springer, Berlin (2013)
9. Fähndrich, J., Ahrndt, S., Albayrak, S.: Self-explanation through semantic annotation: a survey.
In: Position Papers of the 2015 Federated Conference on Computer Science and Information
Systems (FedCSIS) (2015)
10. Fey, G., Drechsler, R.: Self-explaining digital systems—some technical steps. In:
ITG/GI/GMM-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (2019)
11. Fey, G., Staber, S., Bloem, R., Drechsler, R.: Automatic fault localization for property
checking. IEEE Trans. CAD 27(6), 1138–1149 (2008)
12. Fraud, R., Clrot, F.: A methodology to explain neural network classification. Neural Netw.
15(2), 237–246 (2002). https://doi.org/10.1016/S0893-6080(01)00127-7
13. Goldberg, E., Novikov, Y.: Verification of proofs of unsatisfiability for CNF formulas. In:
Design, Automation and Test in Europe, pp. 886–891. IEEE Computer Society, Washington,
DC (2003)
14. Große, D., Kühne, U., Drechsler, R.: Analyzing functional coverage in bounded model
checking. IEEE Trans. CAD 27(7), 1305–1314 (2008)
15. Keng, B., Veneris, A.: Scaling VLSI design debugging with interpolation. In: International
Conference on Formal Methods in CAD, pp. 144–151. IEEE, Piscataway (2009). https://doi.
org/10.1109/FMCAD.2009.5351130
16. Kephart, J.O., Chess, D.M.: The vision of autonomic computing. Computer 36(1), 41–50
(2003)
17. Korel, B., Laski, J.: Dynamic program slicing. Inf. Process. Lett. 29(3), 155–163 (1988).
https://doi.org/10.1016/0020-0190(88)90054-3
18. Lamport, L.: Time, clocks, and the ordering of events in a distributed system. Commun. ACM
21(7), 558–565 (1978). https://doi.org/10.1145/359545.359563
19. Lewis, D.: Causation. J. Philos. 70(17), 556–567 (1973)
20. Liffiton, M., Sakallah, K.: Algorithms for computing minimal unsatisfiable subsets of constraints. J. Autom. Reason. 40(1), 1–33 (2007)
21. Lin, D., Singh, E., Barrett, C., Mitra, S.: A structured approach to post-silicon validation and
debug using symbolic quick error detection. In: 2015 IEEE International Test Conference
(ITC), pp. 1–10. IEEE, Piscataway (2015). https://doi.org/10.1109/TEST.2015.7342397
22. Liu, W.: Real-time fault-tolerant control systems. In: Leondes, C.T. (ed.) Expert Systems,
pp. 267–304. Academic, London (2002)