Index
265
S
Satisfiability Module Theory (SMT), 136,
137
Scoring heuristics, 112, 117–119
analysis, 120–122
asymmetric search tree, 124
average maximum symmetry ratio, 125,
126
benchmark problems, 126–127
characteristics, 129
exploration constants, 127–129
preprocessing approach, 125, 130
sub tree, 125
Self-awareness, 4
Self-complementary (SC) function, 219
Shannon decomposition, 63–64, 137
Shannon theorem, 152, 153
Shor’s algorithm, 21
Side-channel attacks
DPA, 26–27
hiding, 27
masking, 27
timing attacks, 26
Single derivative operation, 72–76
SISTOOL program, 136
Spectral equivalence classes, 204, 207
size distribution, 208, 209
Spectral translations, 198–199
Sum of products (SOPs), 162, 251–252
Switching lattices design
Altun–Riedel method, 160
Boolean function, 161
circuit benchmarks, 161
experimental results, 170–173
four-terminal switches, 159, 160
literal selection, 163–165
MDA, 161
HMDA, 166
offline scheduling problem, 165
polynomial time algorithms, 166
selection strategy, heuristic, 166–167
MPA, 161
benchmarks, 167
BFS tree, 168
HMPA2, 169–170
literals, 168
physical layout, 160
SOPs, 162
synthesis algorithm, 159
Synopsys, 252–257
System verification and validation, 9–10
System Verilog Assertions (SVA), 4
T
Tabular-based methods, 178
Targhi–Unruh variant, 27
Transaction-level explanation, 10
Transformation algorithm, 201–204
True random number generator (TRNG), 40
t-statistic test, 41–42
U
Unit-level explanation, 10
Unit propagation, 108, 114
Upper Confidence Bounds for Trees (UCT)
formula, 109–110
User-understandable explanation, 10
V
Vectorial derivative operation
bent functions, 70, 71
constant function, 70
definitions, 68
IDM, 68, 69
Karnaugh-map, 72
mark functions, 68, 69
representative function, 71
Verification methodology, 4
Verilog modules, 14
Very Large-Scale Integration (VLSI) systems,
177
W
Walsh transform matrix, 85–86
X
XOF, see Extendable-output function
XOR-Majority Graph (XMG), 136
XOR operation, 177
265
S
Satisfiability Module Theory (SMT), 136,
137
Scoring heuristics, 112, 117–119
analysis, 120–122
asymmetric search tree, 124
average maximum symmetry ratio, 125,
126
benchmark problems, 126–127
characteristics, 129
exploration constants, 127–129
preprocessing approach, 125, 130
sub tree, 125
Self-awareness, 4
Self-complementary (SC) function, 219
Shannon decomposition, 63–64, 137
Shannon theorem, 152, 153
Shor’s algorithm, 21
Side-channel attacks
DPA, 26–27
hiding, 27
masking, 27
timing attacks, 26
Single derivative operation, 72–76
SISTOOL program, 136
Spectral equivalence classes, 204, 207
size distribution, 208, 209
Spectral translations, 198–199
Sum of products (SOPs), 162, 251–252
Switching lattices design
Altun–Riedel method, 160
Boolean function, 161
circuit benchmarks, 161
experimental results, 170–173
four-terminal switches, 159, 160
literal selection, 163–165
MDA, 161
HMDA, 166
offline scheduling problem, 165
polynomial time algorithms, 166
selection strategy, heuristic, 166–167
MPA, 161
benchmarks, 167
BFS tree, 168
HMPA2, 169–170
literals, 168
physical layout, 160
SOPs, 162
synthesis algorithm, 159
Synopsys, 252–257
System verification and validation, 9–10
System Verilog Assertions (SVA), 4
T
Tabular-based methods, 178
Targhi–Unruh variant, 27
Transaction-level explanation, 10
Transformation algorithm, 201–204
True random number generator (TRNG), 40
t-statistic test, 41–42
U
Unit-level explanation, 10
Unit propagation, 108, 114
Upper Confidence Bounds for Trees (UCT)
formula, 109–110
User-understandable explanation, 10
V
Vectorial derivative operation
bent functions, 70, 71
constant function, 70
definitions, 68
IDM, 68, 69
Karnaugh-map, 72
mark functions, 68, 69
representative function, 71
Verification methodology, 4
Verilog modules, 14
Very Large-Scale Integration (VLSI) systems,
177
W
Walsh transform matrix, 85–86
X
XOF, see Extendable-output function
XOR-Majority Graph (XMG), 136
XOR operation, 177
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