250
D. Gorodecky and T. Villa
We provide a Verilog functional representation of this example in Listing 11.2
for the modular multiplication of two 6-bit operands by modulo 47.
Listing 11.2 Modular multiplication A · B(mod 47)
module m u l t _ m o d _ 4 7 _ b i t s (A, B , R) ;
i n p u t [ 6 : 1 ] A, B ;
output [ 6 : 1 ] R ;
wire
[ 6 : 1 ] r1 , r2 , r3 , r4 , r5 , r6 ;
wire
[ 8 : 1 ] temp_R_1 ;
wire
[ 7 : 1 ] temp_R_2 ;
reg
[ 6 : 1 ] temp_R ;
mult_3x3 l a b e l 1 ( . a1 (A [ 3 ] ) , . a2 (A [ 2 ] ) , . a3 (A [ 1 ] ) ,
. b1 (B [ 3 ] ) , . b2 (B [ 2 ] ) , . b3 (B [ 1 ] ) ,
. r 1 ( r 1 [ 6 ] ) , . r 2 ( r 1 [ 5 ] ) , . r 3 ( r 1 [ 4 ] ) ,
. r 4 ( r 1 [ 3 ] ) , . r 5 ( r 1 [ 2 ] ) , . r 6 ( r 1 [ 1 ] ) ) ;
mult_3x3_8 l a b e l 2 ( . a1 (A [ 3 ] ) , . a2 (A [ 2 ] ) , . a3 (A [ 1 ] ) ,
. b1 (B [ 6 ] ) , . b2 (B [ 5 ] ) , . b3 (B [ 4 ] ) ,
. r 1 ( r 2 [ 6 ] ) , . r 2 ( r 2 [ 5 ] ) , . r 3 ( r 2 [ 4 ] ) ,
. r 4 ( r 2 [ 3 ] ) , . r 5 ( r 2 [ 2 ] ) , . r 6 ( r 2 [ 1 ] ) ) ;
mult_3x3_8 l a b e l 3 ( . a1 (A [ 6 ] ) , . a2 (A [ 5 ] ) , . a3 (A [ 4 ] ) ,
. b1 (B [ 3 ] ) , . b2 (B [ 2 ] ) , . b3 (B [ 1 ] ) ,
. r 1 ( r 3 [ 6 ] ) , . r 2 ( r 3 [ 5 ] ) , . r 3 ( r 3 [ 4 ] ) ,
. r 4 ( r 3 [ 3 ] ) , . r 5 ( r 3 [ 2 ] ) , . r 6 ( r 3 [ 1 ] ) ) ;
mult_3x3_17 l a b e l 4 ( . a1 (A [ 6 ] ) , . a2 (A [ 5 ] ) , . a3 (A [ 4 ] ) ,
. b1 (B [ 6 ] ) , . b2 (B [ 5 ] ) , . b3 (B [ 4 ] ) ,
. r 1 ( r 4 [ 6 ] ) , . r 2 ( r 4 [ 5 ] ) , . r 3 ( r 4 [ 4 ] ) ,
. r 4 ( r 4 [ 3 ] ) , . r 5 ( r 4 [ 2 ] ) , . r 6 ( r 4 [ 1 ] ) ) ;
a s s i g n temp_R_1 = r 1 + r 2 + r 3 + r 4 ;
mult_3_8 l a b e l 5 ( . a1 ( temp_R_1 [ 6 ] ) , . a2 ( temp_R_1 [ 5 ] ) ,
. a3 ( temp_R_1 [ 4 ] ) ,
. r 1 ( r 5 [ 6 ] ) , . r 2 ( r 5 [ 5 ] ) , . r 3 ( r 5 [ 4 ] ) ,
. r 4 ( r 5 [ 3 ] ) , . r 5 ( r 5 [ 2 ] ) , . r 6 ( r 5 [ 1 ] ) ) ;
mult_2_17 l a b e l 6 ( . a1 ( temp_R_1 [ 8 ] ) , . a2 ( temp_R_1 [ 7 ] ) ,
. r 1 ( r 6 [ 6 ] ) , . r 2 ( r 6 [ 5 ] ) , . r 3 ( r 6 [ 4 ] ) ,
. r 4 ( r 6 [ 3 ] ) , . r 5 ( r 6 [ 2 ] ) , . r 6 ( r 6 [ 1 ] ) ) ;