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6. Chattopadhyay, A., Amarú, L., Soeken, M., Gaillardon, P.E., De Micheli, G.: Notes on majority
Boolean algebra. In: 2016 IEEE 46th International Symposium on Multiple-Valued Logic
(ISMVL), pp. 50–55. IEEE, Sri Lanka (2016)
7. Chu, Z., Soeken, M., Xia, Y., De Micheli, G.: Functional decomposition using majority. In:
Asia and South Pacific Design Automation Conference, pp. 676–681. IEEE, Jeju (2018)
8. Cohn, M., Lindaman, R.: Axiomatic majority-decision logic. IRE Trans. Electron Comput. (1),
17–21 (1961)
9. De Moura, L., Bjørner, N.: Z3: an efficient SMT solver. In: International Conference on Tools
and Algorithms for the Construction and Analysis of Systems, pp. 337–340. Springer, New
York (2008)
10. Karnaugh, M.: The map method for synthesis of combinational logic circuits. Trans. Am. Inst.
Electr. Eng. Part I Commun. Electron. 72(5), 593–599 (1953)
11. Lindaman, R.: A theorem for deriving majority-logic networks within an augmented Boolean
algebra. IRE Trans. Electron. Comp. (3), 338–342 (1960)
12. Mishra, V.K., Thapliyal, H.: Heuristic based majority/minority logic synthesis for emerging
technologies. In: 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), pp. 295–300. IEEE, Jeju (2017)
13. Sasao, T.: Switching Theory for Logic Synthesis, 1st edn. Springer Science & Business Media,
Berlin (2012)
14. Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H.,
Stephan, P.R., Brayton, R.K., Sangiovanni-Vincentelli, A.: Sis: a system for sequential circuit
synthesis. Tech. rep., EECS Department, University of California, CA (1992). http://www2.
eecs.berkeley.edu/Pubs/TechRpts/1992/2010.html
15. Shannon, C.E.: The synthesis of two-terminal switching circuits. Bell Syst. Tech. J. 28(1),
59–98 (1949)
16. Soeken, M., Amaru, L.G., Gaillardon, P.E., De Micheli, G.: Exact synthesis of majorityinverter graphs and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
36(11), 1842–1855 (2017)
17. Soeken, M., Haaswijk, W., Testa, E., Mishchenko, A., Amarù, L.G., Brayton, R.K., De Micheli,
G.: Practical exact synthesis. In: 2018 Design, Automation and Test in Europe Conference and
Exhibition (DATE), pp. 309–314. IEEE, Dresden (2018)
18. Walus, K., Schulhof, G., Jullien, G., Zhang, R., Wang, W.: Circuit design based on majority gates for applications with quantum-dot cellular automata. In: Conference Record of
the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers 2004, vol. 2,
pp. 1354–1357. IEEE, Dresden (2004)
19. Wang, P., Niamat, M., Vemuru, S.: Minimal majority gate mapping of 4-variable functions
for quantum cellular automata. In: 2011 11th IEEE Conference on Nanotechnology (IEEENANO), pp. 1307–1312. IEEE, Dresden (2011)
20. Wang, P., Niamat, M.Y., Vemuru, S.R., Alam, M., Killian, T.: Synthesis of majority/minority
logic networks. IEEE Trans. Nanotechnol. 14(3), 473–483 (2015)
21. Zhang, R., Walus, K., Wang, W., Jullien, G.A.: A method of majority logic reduction for
quantum cellular automata. IEEE Trans. Nanotechnol. 3(4), 443–450 (2004)
22. Zhang, R., Gupta, P., Jha, N.K.: Majority and minority network synthesis with application
to QCA-, SET-, and TPL-based nanotechnologies. IEEE Trans. Comput. Aided Des. Integr.
Circuits Syst. 26(7), 1233–1245 (2007)
E. C. Ferraz et al.
6. Chattopadhyay, A., Amarú, L., Soeken, M., Gaillardon, P.E., De Micheli, G.: Notes on majority
Boolean algebra. In: 2016 IEEE 46th International Symposium on Multiple-Valued Logic
(ISMVL), pp. 50–55. IEEE, Sri Lanka (2016)
7. Chu, Z., Soeken, M., Xia, Y., De Micheli, G.: Functional decomposition using majority. In:
Asia and South Pacific Design Automation Conference, pp. 676–681. IEEE, Jeju (2018)
8. Cohn, M., Lindaman, R.: Axiomatic majority-decision logic. IRE Trans. Electron Comput. (1),
17–21 (1961)
9. De Moura, L., Bjørner, N.: Z3: an efficient SMT solver. In: International Conference on Tools
and Algorithms for the Construction and Analysis of Systems, pp. 337–340. Springer, New
York (2008)
10. Karnaugh, M.: The map method for synthesis of combinational logic circuits. Trans. Am. Inst.
Electr. Eng. Part I Commun. Electron. 72(5), 593–599 (1953)
11. Lindaman, R.: A theorem for deriving majority-logic networks within an augmented Boolean
algebra. IRE Trans. Electron. Comp. (3), 338–342 (1960)
12. Mishra, V.K., Thapliyal, H.: Heuristic based majority/minority logic synthesis for emerging
technologies. In: 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), pp. 295–300. IEEE, Jeju (2017)
13. Sasao, T.: Switching Theory for Logic Synthesis, 1st edn. Springer Science & Business Media,
Berlin (2012)
14. Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H.,
Stephan, P.R., Brayton, R.K., Sangiovanni-Vincentelli, A.: Sis: a system for sequential circuit
synthesis. Tech. rep., EECS Department, University of California, CA (1992). http://www2.
eecs.berkeley.edu/Pubs/TechRpts/1992/2010.html
15. Shannon, C.E.: The synthesis of two-terminal switching circuits. Bell Syst. Tech. J. 28(1),
59–98 (1949)
16. Soeken, M., Amaru, L.G., Gaillardon, P.E., De Micheli, G.: Exact synthesis of majorityinverter graphs and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
36(11), 1842–1855 (2017)
17. Soeken, M., Haaswijk, W., Testa, E., Mishchenko, A., Amarù, L.G., Brayton, R.K., De Micheli,
G.: Practical exact synthesis. In: 2018 Design, Automation and Test in Europe Conference and
Exhibition (DATE), pp. 309–314. IEEE, Dresden (2018)
18. Walus, K., Schulhof, G., Jullien, G., Zhang, R., Wang, W.: Circuit design based on majority gates for applications with quantum-dot cellular automata. In: Conference Record of
the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers 2004, vol. 2,
pp. 1354–1357. IEEE, Dresden (2004)
19. Wang, P., Niamat, M., Vemuru, S.: Minimal majority gate mapping of 4-variable functions
for quantum cellular automata. In: 2011 11th IEEE Conference on Nanotechnology (IEEENANO), pp. 1307–1312. IEEE, Dresden (2011)
20. Wang, P., Niamat, M.Y., Vemuru, S.R., Alam, M., Killian, T.: Synthesis of majority/minority
logic networks. IEEE Trans. Nanotechnol. 14(3), 473–483 (2015)
21. Zhang, R., Walus, K., Wang, W., Jullien, G.A.: A method of majority logic reduction for
quantum cellular automata. IEEE Trans. Nanotechnol. 3(4), 443–450 (2004)
22. Zhang, R., Gupta, P., Jha, N.K.: Majority and minority network synthesis with application
to QCA-, SET-, and TPL-based nanotechnologies. IEEE Trans. Comput. Aided Des. Integr.
Circuits Syst. 26(7), 1233–1245 (2007)