implemented using hardware or system software or their combinations. Thus, reliability gain might be achieved by combination of both methods.
4.6.1 Hardware Redundancy: Reliability Analysis
We introduce a reliability value for each hardware component and assume a
Poisson failure rate k to calculate the overall reliability of the whole system, as it
was introduced in previous chapters.
If time redundancy is used to implement one or more steps of GAFT, we can use
the overhead of the redundancy solution to give an estimation of the performance
degradation caused by the introduced redundancy.
If the additional required cost to develop and manufacture a fault tolerance
feature is taken into consideration as well, it is possible to quantitatively evaluate
and compare different approaches to implement fault tolerance.
Next, we derive a model to analyze the achievable reliability of possible processor and memory structures and to predict how long and at what availability level
such a solution can operate [9].
We denote the permanent fault rate of a processor without redundancy as k pfl and
the transient fault rate as k ifl . The probability of operation without fault within the
time frame [0, T] is determined by
Fig. 4.5 Efficiency of a system with faults and checking schemes
4.6 Hardware Redundancy and Reliability
39
4.6.1 Hardware Redundancy: Reliability Analysis
We introduce a reliability value for each hardware component and assume a
Poisson failure rate k to calculate the overall reliability of the whole system, as it
was introduced in previous chapters.
If time redundancy is used to implement one or more steps of GAFT, we can use
the overhead of the redundancy solution to give an estimation of the performance
degradation caused by the introduced redundancy.
If the additional required cost to develop and manufacture a fault tolerance
feature is taken into consideration as well, it is possible to quantitatively evaluate
and compare different approaches to implement fault tolerance.
Next, we derive a model to analyze the achievable reliability of possible processor and memory structures and to predict how long and at what availability level
such a solution can operate [9].
We denote the permanent fault rate of a processor without redundancy as k pfl and
the transient fault rate as k ifl . The probability of operation without fault within the
time frame [0, T] is determined by
Fig. 4.5 Efficiency of a system with faults and checking schemes
4.6 Hardware Redundancy and Reliability
39