found in http://plato.stanford.edu/entries/turing-machine/. What is missing in turing
or Von Neumann architectures is an answer how and when algorithm and data were
placed into the memory (tape in Turing machine). Besides, arrow on the figure is
assumed to connect but not explained how this communication is executed.
17.5.1 Hardware Zones
Thus, from information processing point of view, we have even from this simple
picture involvement of three zones (Fig. 17.9):
• active zone,
• interface zone, and
• passive zone.
Active zone (AZ) includes schemes that change information (processors, converters). Interface zone (IZ) includes schemes that transfer information from external
source or between AZ and PZ (internal source). Finally, passive zone (PZ) includes
schemes that save or store information.
What is missing in the previous picture? To make any information processing
model useful, we have to introduce input and output options for information.
Each AZ, PZ, and IZ might be active in terms of data flow control (so far not
processing) flags—demand of service, interruption request, message writing/
sending requests, etc. Let us have a look at Fig. 17.10.
All arrows might be different in speed, and use various frequencies and bandwidths, bit size (8, 12, 24, 36, 48, 64, 128) procedures of control, and data delivery
(parallel, sequential). This is still not self-explanatory how we deal with information
exchange. More realistic figure is presented in Fig. 17.11.
Level of information interaction AZ, PZ, or IZ actually defines structure of the
system similar to Flynn diagram (find what is it, dear reader, it might be useful).
In terms of input and output examples of implementation of each zone, one
might suggest the following:
AZ inputs and outputs iAZ and oAZ:
• register content exchange between processors,
• signal write or read to interrupt processor execution,
• mutual exclusion efficiency of multiprocessor communication, and
INTERFACE
ZONE
PASSIVE
ZONE
ACTIVE
ZONE
Fig. 17.9 Hardware
segments of CA of
information processing
228
17 On Performance: From Hardware up to Distributed Systems
or Von Neumann architectures is an answer how and when algorithm and data were
placed into the memory (tape in Turing machine). Besides, arrow on the figure is
assumed to connect but not explained how this communication is executed.
17.5.1 Hardware Zones
Thus, from information processing point of view, we have even from this simple
picture involvement of three zones (Fig. 17.9):
• active zone,
• interface zone, and
• passive zone.
Active zone (AZ) includes schemes that change information (processors, converters). Interface zone (IZ) includes schemes that transfer information from external
source or between AZ and PZ (internal source). Finally, passive zone (PZ) includes
schemes that save or store information.
What is missing in the previous picture? To make any information processing
model useful, we have to introduce input and output options for information.
Each AZ, PZ, and IZ might be active in terms of data flow control (so far not
processing) flags—demand of service, interruption request, message writing/
sending requests, etc. Let us have a look at Fig. 17.10.
All arrows might be different in speed, and use various frequencies and bandwidths, bit size (8, 12, 24, 36, 48, 64, 128) procedures of control, and data delivery
(parallel, sequential). This is still not self-explanatory how we deal with information
exchange. More realistic figure is presented in Fig. 17.11.
Level of information interaction AZ, PZ, or IZ actually defines structure of the
system similar to Flynn diagram (find what is it, dear reader, it might be useful).
In terms of input and output examples of implementation of each zone, one
might suggest the following:
AZ inputs and outputs iAZ and oAZ:
• register content exchange between processors,
• signal write or read to interrupt processor execution,
• mutual exclusion efficiency of multiprocessor communication, and
INTERFACE
ZONE
PASSIVE
ZONE
ACTIVE
ZONE
Fig. 17.9 Hardware
segments of CA of
information processing
228
17 On Performance: From Hardware up to Distributed Systems