234
M. Tsuji et.al.
Fig. 14 Overview of fault tolerance in the mSPMD programming model
Table 5 Specification of a
FX10 cluster
CPU
Fujitsu SPARC64VIIIIfx, 16 core, 1.65 GHz
Memory 32 GB, 85 GB/s
Cache
L1: 32 + 32 KB/core, L2: 6 MB/core
Network Tofu (6D mesh/torus) Interconnect
5 GB/s × 2
M. Tsuji et.al.
Fig. 14 Overview of fault tolerance in the mSPMD programming model
Table 5 Specification of a
FX10 cluster
CPU
Fujitsu SPARC64VIIIIfx, 16 core, 1.65 GHz
Memory 32 GB, 85 GB/s
Cache
L1: 32 + 32 KB/core, L2: 6 MB/core
Network Tofu (6D mesh/torus) Interconnect
5 GB/s × 2