614
M. Delfino
and the performance perceived by the user is the rate of completion of tasks, or
“throughput”. This type of computing is complimentary to “High Performance
Computing” (HPC), i.e. the execution of a single task at maximum speed on
a classical supercomputer. The particular case of event or collision processing
requiring little inter-processor communication is an example of “loosely coupled
parallel computing” or even “embarrassingly parallel computing”. 2,3 Certain kinds
of accelerator simulations, particularly those that use ray-tracing techniques, can
also be executed as distributed computing tasks. Multiple computer systems can
also be interconnected in “tightly-bound” configurations via low-latency networks, 4
essentially yielding a supercomputer. Tightly-bound systems are used in particle
physics, for example, for solving equations from theories using numerical methods
(e.g. lattice-gauge theories); they are mentioned here for completeness and will not
be covered further.
From the decade of the 2010s, the boundary between HTC and HPC has started
to blur, for a number of disparate reasons:
Multi-core Applications Detectors have become more complex and have more
channels. This impacts the memory footprint of reconstruction, simulation and
analysis programs, which has grown substantially. In parallel, processors have
become multi-core 5 with shared RAM. 6 The growth in number of cores per
processor has been faster than the drop in price of RAM chips, resulting in an
effective memory shortage. This means that running an independent copy of the
operating system and the application in each core is not economical. The way
out is to implement the safe execution of parallel threads 7 of a single copy of the
program on each multi-core processor. This introduces a number of dependencies,
for example competition for RAM and for input–output services, that break the
loose coupling and make the applications behave more like HPC programs.
2 Wilkinson, Barry, and Michael Allen. Parallel programming. Pearson India, 2004.
3 Birrittella, Mark S., et al. “Intel
® Omni-path architecture: Enabling scalable, high performance
fabrics.” High-Performance Interconnects (HOTI), 2015 IEEE 23rd Annual Symposium on. IEEE,
2015.
4 Pfister, Gregory F. “An introduction to the infiniband architecture.” High Performance Mass
Storage and Parallel I/O 42 (2001): 617–632.
5 A core corresponds to the Central Processing Unit (CPU) of a classical computer, which is able
to execute a single stream of instructions. Technology allows a growing number of ever smaller
transistors to be placed on a single chip. However, profiting from these large number of transistors
in a single core design would require prohibitively complex processor designs and impossible
to achieve clock speeds. The alternative is to populate the chips with many copies of the same
processor core, which work independently except for sharing external connections, leading to
multi-core processors. Gepner, Pawel, and Michal Filip Kowalik. “Multi-core processors: New
way to achieve high system performance.” Parallel Computing in Electrical Engineering, 2006.
PAR ELEC 2006. International Symposium on. IEEE, 2006.
6 Random Access Memory, the external solid state memory used by a processor.
7 A thread is a stream of processing instructions coming from a shared program image which has its
own private data instances in processor hardware registers, instruction and data stack and caches,
and RAM.
M. Delfino
and the performance perceived by the user is the rate of completion of tasks, or
“throughput”. This type of computing is complimentary to “High Performance
Computing” (HPC), i.e. the execution of a single task at maximum speed on
a classical supercomputer. The particular case of event or collision processing
requiring little inter-processor communication is an example of “loosely coupled
parallel computing” or even “embarrassingly parallel computing”. 2,3 Certain kinds
of accelerator simulations, particularly those that use ray-tracing techniques, can
also be executed as distributed computing tasks. Multiple computer systems can
also be interconnected in “tightly-bound” configurations via low-latency networks, 4
essentially yielding a supercomputer. Tightly-bound systems are used in particle
physics, for example, for solving equations from theories using numerical methods
(e.g. lattice-gauge theories); they are mentioned here for completeness and will not
be covered further.
From the decade of the 2010s, the boundary between HTC and HPC has started
to blur, for a number of disparate reasons:
Multi-core Applications Detectors have become more complex and have more
channels. This impacts the memory footprint of reconstruction, simulation and
analysis programs, which has grown substantially. In parallel, processors have
become multi-core 5 with shared RAM. 6 The growth in number of cores per
processor has been faster than the drop in price of RAM chips, resulting in an
effective memory shortage. This means that running an independent copy of the
operating system and the application in each core is not economical. The way
out is to implement the safe execution of parallel threads 7 of a single copy of the
program on each multi-core processor. This introduces a number of dependencies,
for example competition for RAM and for input–output services, that break the
loose coupling and make the applications behave more like HPC programs.
2 Wilkinson, Barry, and Michael Allen. Parallel programming. Pearson India, 2004.
3 Birrittella, Mark S., et al. “Intel
® Omni-path architecture: Enabling scalable, high performance
fabrics.” High-Performance Interconnects (HOTI), 2015 IEEE 23rd Annual Symposium on. IEEE,
2015.
4 Pfister, Gregory F. “An introduction to the infiniband architecture.” High Performance Mass
Storage and Parallel I/O 42 (2001): 617–632.
5 A core corresponds to the Central Processing Unit (CPU) of a classical computer, which is able
to execute a single stream of instructions. Technology allows a growing number of ever smaller
transistors to be placed on a single chip. However, profiting from these large number of transistors
in a single core design would require prohibitively complex processor designs and impossible
to achieve clock speeds. The alternative is to populate the chips with many copies of the same
processor core, which work independently except for sharing external connections, leading to
multi-core processors. Gepner, Pawel, and Michal Filip Kowalik. “Multi-core processors: New
way to achieve high system performance.” Parallel Computing in Electrical Engineering, 2006.
PAR ELEC 2006. International Symposium on. IEEE, 2006.
6 Random Access Memory, the external solid state memory used by a processor.
7 A thread is a stream of processing instructions coming from a shared program image which has its
own private data instances in processor hardware registers, instruction and data stack and caches,
and RAM.