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W. H. Smith
calorimeter and muon triggers. The CMS HLT output rate to storage will range
between 5 and 7.5 kHz for pileup ranging between 140 and 200.
The hardware implementations of the HL-LHC ATLAS and CMS L1T will
use high-bandwidth serial I/O links for data communication and large, modern
field-programmable gate arrays (FPGAs) for sophisticated and fast algorithms. The
development and synthesis of FPGA firmware incorporating these algorithms is
significantly enhanced in reliability, accessibility and performance with Higher
Level Synthesis (HLS) tools [31]. The latest developments and expectations for
future FPGAs not only include significant increases in the number of logic gates
available and high-speed serial links, but also increases in the number of highbandwidth serial links per device, more sophisticated and fast DSPs, embedded
Linux, and integration with high speed networking. Fast Tracking Trigger devices
such as the ATLAS FTK [25] use Associative Memories. The hardware framework
will be designed following standards deployed in industry, such as the Advanced
Telecommunications Architecture (ATCA) for backplanes, which offers substantial
backplane bandwidth and flexibility and provides for users to extend the backplane
connectivity using the spare I/O available on each card. Further interconnectivity
technology developments such as optical backplanes and wireless data transmission
may provide additional opportunities.
The increase in L1 output rate from 100 kHz to possibly as high as 1 MHz
requires higher bandwidth into the DAQ system and more CPU power in the HLT.
The addition of a tracking trigger and more sophisticated algorithms at L1 increases
the purity of the sample of events passing the L1 trigger, but requires a higher
sophistication and complexity of algorithms used at the HLT. This implies a greater
CPU power than scaling with the L1 output rate but is somewhat mitigated by the
availability of the L1 Tracking Trigger primitives in the data immediately accessible
by the HLT. Without a L1 tracking trigger, the opportunity to access most of the
tracker information at the first levels of the HLT is limited by the CPU time to
unpack and reconstruct the tracking data. This is significantly improved in the
ATLAS FTK that provides quick access to tracking information in the HLT. For
the HL-LHC, the addition of the L1 tracking trigger means that the results from the
L1T track reconstruction can be immediately used without the overhead of tracking
data unpacking and reconstruction.
The evolution of the computing market towards different computing platforms
and co-processors offers an opportunity to achieve substantial gains in HLT
processing power at the price of adapting code to the new hardware. Examples
include Graphical Processor Units (GPUs), such as the NVIDIA Tesla and GeForce
(used by ALICE [32]), ARM processors, FPGAs (e.g. the Xeon/FPGA used by
LHCb [33]) and the Intel Xeon Phi coprocessor. Additional HLT processing power
may result from improved code such as machine learning algorithms for track
reconstruction [34].
W. H. Smith
calorimeter and muon triggers. The CMS HLT output rate to storage will range
between 5 and 7.5 kHz for pileup ranging between 140 and 200.
The hardware implementations of the HL-LHC ATLAS and CMS L1T will
use high-bandwidth serial I/O links for data communication and large, modern
field-programmable gate arrays (FPGAs) for sophisticated and fast algorithms. The
development and synthesis of FPGA firmware incorporating these algorithms is
significantly enhanced in reliability, accessibility and performance with Higher
Level Synthesis (HLS) tools [31]. The latest developments and expectations for
future FPGAs not only include significant increases in the number of logic gates
available and high-speed serial links, but also increases in the number of highbandwidth serial links per device, more sophisticated and fast DSPs, embedded
Linux, and integration with high speed networking. Fast Tracking Trigger devices
such as the ATLAS FTK [25] use Associative Memories. The hardware framework
will be designed following standards deployed in industry, such as the Advanced
Telecommunications Architecture (ATCA) for backplanes, which offers substantial
backplane bandwidth and flexibility and provides for users to extend the backplane
connectivity using the spare I/O available on each card. Further interconnectivity
technology developments such as optical backplanes and wireless data transmission
may provide additional opportunities.
The increase in L1 output rate from 100 kHz to possibly as high as 1 MHz
requires higher bandwidth into the DAQ system and more CPU power in the HLT.
The addition of a tracking trigger and more sophisticated algorithms at L1 increases
the purity of the sample of events passing the L1 trigger, but requires a higher
sophistication and complexity of algorithms used at the HLT. This implies a greater
CPU power than scaling with the L1 output rate but is somewhat mitigated by the
availability of the L1 Tracking Trigger primitives in the data immediately accessible
by the HLT. Without a L1 tracking trigger, the opportunity to access most of the
tracker information at the first levels of the HLT is limited by the CPU time to
unpack and reconstruct the tracking data. This is significantly improved in the
ATLAS FTK that provides quick access to tracking information in the HLT. For
the HL-LHC, the addition of the L1 tracking trigger means that the results from the
L1T track reconstruction can be immediately used without the overhead of tracking
data unpacking and reconstruction.
The evolution of the computing market towards different computing platforms
and co-processors offers an opportunity to achieve substantial gains in HLT
processing power at the price of adapting code to the new hardware. Examples
include Graphical Processor Units (GPUs), such as the NVIDIA Tesla and GeForce
(used by ALICE [32]), ARM processors, FPGAs (e.g. the Xeon/FPGA used by
LHCb [33]) and the Intel Xeon Phi coprocessor. Additional HLT processing power
may result from improved code such as machine learning algorithms for track
reconstruction [34].