Preface................................................................................................................... xiii
Authors ................................................................................................................ xvii
1. Introduction .....................................................................................................1
1.1 System-on-Chip Integration and Its Challenges ..............................1
1.2 SoC to Network-on-Chip: A Paradigm Shift.....................................3
1.3 Research Issues in NoC Development ...............................................5
1.4 Existing NoC Examples .......................................................................8
1.5 Summary.............................................................................................. 10
References ....................................................................................................... 10
2. Interconnection Networks in Network-on-Chip ................................... 13
2.1 Introduction ......................................................................................... 13
2.2 Network Topologies............................................................................ 14
2.2.1 Number of Edges ................................................................... 25
2.2.2 Average Distance ................................................................... 25
2.3 Switching Techniques......................................................................... 29
2.4 Routing Strategies ...............................................................................30
2.4.1 Routing-Dependent Deadlock ............................................. 31
2.4.1.1
Deterministic Routing in M × N MoT
Network ...............................................................33
2.4.2 Avoidance of Message-Dependent Deadlock .................... 41
2.5 Flow Control Protocol.........................................................................43
2.6 Quality-of-Service Support................................................................ 45
2.7 NI Module ............................................................................................ 46
2.8 Summary.............................................................................................. 48
References ....................................................................................................... 48
3. Architecture Design of Network-on-Chip .............................................. 53
3.1 Introduction ......................................................................................... 53
3.2 Switching Techniques and Packet Format ...................................... 53
3.3 Asynchronous FIFO Design ..............................................................54
3.4 GALS Style of Communication ......................................................... 57
3.5 Wormhole Router Architecture Design........................................... 57
3.5.1 Input Channel Module.......................................................... 58
3.5.2 Output Channel Module ...................................................... 58
3.6 VC Router Architecture Design ........................................................63
3.6.1 Input Channel Module..........................................................65
3.6.2 Output Links .......................................................................... 66
Contents
v
Authors ................................................................................................................ xvii
1. Introduction .....................................................................................................1
1.1 System-on-Chip Integration and Its Challenges ..............................1
1.2 SoC to Network-on-Chip: A Paradigm Shift.....................................3
1.3 Research Issues in NoC Development ...............................................5
1.4 Existing NoC Examples .......................................................................8
1.5 Summary.............................................................................................. 10
References ....................................................................................................... 10
2. Interconnection Networks in Network-on-Chip ................................... 13
2.1 Introduction ......................................................................................... 13
2.2 Network Topologies............................................................................ 14
2.2.1 Number of Edges ................................................................... 25
2.2.2 Average Distance ................................................................... 25
2.3 Switching Techniques......................................................................... 29
2.4 Routing Strategies ...............................................................................30
2.4.1 Routing-Dependent Deadlock ............................................. 31
2.4.1.1
Deterministic Routing in M × N MoT
Network ...............................................................33
2.4.2 Avoidance of Message-Dependent Deadlock .................... 41
2.5 Flow Control Protocol.........................................................................43
2.6 Quality-of-Service Support................................................................ 45
2.7 NI Module ............................................................................................ 46
2.8 Summary.............................................................................................. 48
References ....................................................................................................... 48
3. Architecture Design of Network-on-Chip .............................................. 53
3.1 Introduction ......................................................................................... 53
3.2 Switching Techniques and Packet Format ...................................... 53
3.3 Asynchronous FIFO Design ..............................................................54
3.4 GALS Style of Communication ......................................................... 57
3.5 Wormhole Router Architecture Design........................................... 57
3.5.1 Input Channel Module.......................................................... 58
3.5.2 Output Channel Module ...................................................... 58
3.6 VC Router Architecture Design ........................................................63
3.6.1 Input Channel Module..........................................................65
3.6.2 Output Links .......................................................................... 66
Contents
v
