Index
367
Single-chip cloud computer (SCC), 9
Single error correction (SEC), 220
Single-event transient (SET) pulse, 201
Single-event upset (SEU), 200
Soft error rate (SER), 201
Soft errors, 199–203
in back-to-back inverter, 200, 200f
classification of effect, 201
correction, 206–210
combinational logic, 207–210,
208f, 209f
in latches, 207f
using time-shifted output, 209f
in D-type latch, 200, 201f
Sort-based mapping (SBMAP), 139
STALL/GO flow control protocol, 44, 44f
Static voltage scaling (SVS), 160
Store-and-forward (SAF) packet
switching techniques, 29
Subthreshold leakage current (I sub ), 156
Swap operation, 259–260
Switch allocation, 64
Switch arbiter (SA), 58, 205
Switching power consumption, 155–156
Switching techniques, 29–30
and packet format, 53–54, 54f
Switch-to-switch flow control
schemes, 218
System-level floorplanning, 268–271
constraints, 269–270
mesh topology constraints,
270–271, 270f
objective function, 269
variables
dependent, 268–269
independent, 268
System-level power reduction, 172–188
DFS, 179–185
characteristics, 184t
DFS algorithm, 183
history-based DFS, 181–182, 182f
link controller, 183–184
DVS, 172–179
characteristics, 173
components of links, 173f
hardware implementation, 178, 178f
history-based DVS, 174–178
runtime power gating, 186–188, 188f
VFI partitioning, 185–186
System-on-chip (SoC), 1, 75, 129, 191, 235,
319, 321
categories, 1
hand mapping of cores in four-
layered 3D, 349, 349t
integration and its challenges, 1–2
to NoC, 3–5
T
TD factor, 202
Template-based efficient mapping
(TEM) algorithm, 139
T-Error flow control protocol, 44, 45f
Test access mechanism (TAM), 235
Three-dimensional (3D) NoC, 317
Three-wire model
energy obtained from HSPICE, 82t
parasitic capacitance, inductance,
and resistance of, 81t
Throughput, 78
vs. locality factor, 85–86, 87f, 98–99,
98f, 109–110, 110f, 341–342, 341t
vs. offered load, 104, 105f
Through-silicon vias (TSVs), 8, 317, 319
misalignments, 322, 322f
Time division multiplexed access
(TDMA), 138
Time division multiplexing (TDW), 354
Topology graph, 120, 122
Topology reconfiguration, 304–311,
308f, 309f
architecture, 306–311
application mapping, 307–308
core-to-network mapping,
309–310
and route generation, 310–311
routers wrapped by
switches, 305f
logical, 306f
modification around routers, 305
multiplexer-based implementation,
307f
Traffic modeling, 81–84
Transient fault controlling techniques
inter-router link error control,
210–221
capacitive crosstalk avoidance
techniques, 210–216
367
Single-chip cloud computer (SCC), 9
Single error correction (SEC), 220
Single-event transient (SET) pulse, 201
Single-event upset (SEU), 200
Soft error rate (SER), 201
Soft errors, 199–203
in back-to-back inverter, 200, 200f
classification of effect, 201
correction, 206–210
combinational logic, 207–210,
208f, 209f
in latches, 207f
using time-shifted output, 209f
in D-type latch, 200, 201f
Sort-based mapping (SBMAP), 139
STALL/GO flow control protocol, 44, 44f
Static voltage scaling (SVS), 160
Store-and-forward (SAF) packet
switching techniques, 29
Subthreshold leakage current (I sub ), 156
Swap operation, 259–260
Switch allocation, 64
Switch arbiter (SA), 58, 205
Switching power consumption, 155–156
Switching techniques, 29–30
and packet format, 53–54, 54f
Switch-to-switch flow control
schemes, 218
System-level floorplanning, 268–271
constraints, 269–270
mesh topology constraints,
270–271, 270f
objective function, 269
variables
dependent, 268–269
independent, 268
System-level power reduction, 172–188
DFS, 179–185
characteristics, 184t
DFS algorithm, 183
history-based DFS, 181–182, 182f
link controller, 183–184
DVS, 172–179
characteristics, 173
components of links, 173f
hardware implementation, 178, 178f
history-based DVS, 174–178
runtime power gating, 186–188, 188f
VFI partitioning, 185–186
System-on-chip (SoC), 1, 75, 129, 191, 235,
319, 321
categories, 1
hand mapping of cores in four-
layered 3D, 349, 349t
integration and its challenges, 1–2
to NoC, 3–5
T
TD factor, 202
Template-based efficient mapping
(TEM) algorithm, 139
T-Error flow control protocol, 44, 45f
Test access mechanism (TAM), 235
Three-dimensional (3D) NoC, 317
Three-wire model
energy obtained from HSPICE, 82t
parasitic capacitance, inductance,
and resistance of, 81t
Throughput, 78
vs. locality factor, 85–86, 87f, 98–99,
98f, 109–110, 110f, 341–342, 341t
vs. offered load, 104, 105f
Through-silicon vias (TSVs), 8, 317, 319
misalignments, 322, 322f
Time division multiplexed access
(TDMA), 138
Time division multiplexing (TDW), 354
Topology graph, 120, 122
Topology reconfiguration, 304–311,
308f, 309f
architecture, 306–311
application mapping, 307–308
core-to-network mapping,
309–310
and route generation, 310–311
routers wrapped by
switches, 305f
logical, 306f
modification around routers, 305
multiplexer-based implementation,
307f
Traffic modeling, 81–84
Transient fault controlling techniques
inter-router link error control,
210–221
capacitive crosstalk avoidance
techniques, 210–216