336
Network-on-Chip
However, the TSV process does not scale with the CMOS technology. TSV
diameters and pitches are 2–3 times bigger than transistor gate lengths. This
implies that, even moving to newer technologies, the intrinsic cost for vertical interconnect does not change. For this geometry and sizing, the TSV
inductance and inductive coupling becomes negligible and the intrinsic TSV
delay can be assumed as a function of resistance and capacitance only.
Routers for all the above-mentioned networks have been designed in
Verilog HDL and synthesized using Synopsys Design Vision supporting 90 nm
technology. For a specific network, critical path delay of a router increases
as the routing logic and arbitration complexity increase with increasing
connectivity. Hence, in a network, the router with the highest connectivity
has the minimum frequency. To support mesochronous clocking, the clock
with the minimum frequency is applied to all the routers of a network.
Table  11.2 depicts the clock frequencies of the routers used in the middle
layers of the 3D NoC structures under consideration. Due to their least connectivity requirements, MoT routers can run at a higher frequency compared
to others. However, in this work, to provide a consistent comparison with
other networks, all the routers are driven at 1.5 GHz clock. The worst-case
link delay (as shown in Chapter 4) is much lesser than the router clock period
of 666 ps. The delay of interlayer vias and the links having a length of tens
of microns is also very less. Hence, those links do not come into the critical
path of the overall NoC.
11.3.2.1 Network Area Estimation
Table 11.2 contains the silicon area required by each type of router from its
gate-level netlist to implement the middle layer of different four-layered
3D NoCs by taking 32-bit flit size. For a fair comparison of the networks,
this section revisits all the four-layered networks taken here into consideration. Although the dimension of each tile is taken as a square of side
2.5 mm, inter-tile spacing in each layer varies significantly with underlying
topology due to varying sizes of routers, which in turn causes variations in
layer dimension. For larger network dimension in each layer, the number
of links running through inter-tile spaces of a specific layer varies in different networks. For larger number of cores in a single layer, while mesh
structure (both Mesh-1 and Mesh-2) has uniform wiring density, MoT and
BFT have nonuniform wire densities in each layer and use flyover links
over the top of another router as shown in Chapter 4. Thus, to compare the
dimension of the middle layer in different topologies, this work has taken
uniform channel width of 32 bits for all the networks. The width of each
wire and inter-wire spacing are taken to be the same and equal to 0.25 µm,
as mentioned earlier. The dimension of each router is assumed to be a perfect square.
The dimensions of the middle layer of a mesh-based network can be
estimated as follows: The routers in each row are placed between two