9
Application-Specific
Network- on-Chip Synthesis
9.1 Introduction
The network-on-chip architectures, discussed so far in the book, are developed
around regular topologies, with the inherent assumption that the cores are
all of equal size. The main advantage of such a regular NoC architecture is
topology reuse and reduced design time. The assumptions of equal core size
and communication bandwidth requirement hold for homogeneous cores.
However, application-specific system-on-chip (SoC) architectures, in general, contain heterogeneous cores and memory elements with widely varying
sizes. Hence, even though the system-level NoC architecture is regular, after
floorplanning the final topology becomes irregular. Maintaining a regular
structure at this level of layout necessitates large area overhead. The links
also become longer, resulting in increase in delay and power consumption
in them. This necessitates looking for alternative NoC topologies, specific for
the application. Such NoCs are known as application-specific NoC (ASNoC).
ASNoC provides the facility to incorporate custom NoC architectures, optimized for the target problem domain. It is not necessary to conform to any
regular topology. As a result, ASNoCs often provide architectures superior
to the regular ones, in terms of power and area consumption under identical
performance requirements. The routers can also be parameterized (such as
the number of ports, the physical link length and width, and the number of
virtual channels), and thus can be reused in the design.
In ASNoC synthesis, the application is specified as a set of tasks with different communication requirements between them. The tasks are mapped
onto a computation architecture. The computation architecture consists of a
set of processing and memory cores. The tasks are distributed among the
processing cores. As a result, the cores now need to communicate between
themselves.
263
Application-Specific
Network- on-Chip Synthesis
9.1 Introduction
The network-on-chip architectures, discussed so far in the book, are developed
around regular topologies, with the inherent assumption that the cores are
all of equal size. The main advantage of such a regular NoC architecture is
topology reuse and reduced design time. The assumptions of equal core size
and communication bandwidth requirement hold for homogeneous cores.
However, application-specific system-on-chip (SoC) architectures, in general, contain heterogeneous cores and memory elements with widely varying
sizes. Hence, even though the system-level NoC architecture is regular, after
floorplanning the final topology becomes irregular. Maintaining a regular
structure at this level of layout necessitates large area overhead. The links
also become longer, resulting in increase in delay and power consumption
in them. This necessitates looking for alternative NoC topologies, specific for
the application. Such NoCs are known as application-specific NoC (ASNoC).
ASNoC provides the facility to incorporate custom NoC architectures, optimized for the target problem domain. It is not necessary to conform to any
regular topology. As a result, ASNoCs often provide architectures superior
to the regular ones, in terms of power and area consumption under identical
performance requirements. The routers can also be parameterized (such as
the number of ports, the physical link length and width, and the number of
virtual channels), and thus can be reused in the design.
In ASNoC synthesis, the application is specified as a set of tasks with different communication requirements between them. The tasks are mapped
onto a computation architecture. The computation architecture consists of a
set of processing and memory cores. The tasks are distributed among the
processing cores. As a result, the cores now need to communicate between
themselves.
263