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Network-on-Chip
5.6.6 Other evolutionary Approaches
A two-step GA for mapping applications onto NoC was proposed by Lei and
Kumar (2003), which reduces the overall execution time. In the first step, the
tasks are assigned onto different IPs assuming the edge delays to be constant
and equal to the average edge delay. In the second step, the IPs are mapped to
tiles of NoC taking the actual edge delay, based on the network traffic model,
and the total system delay is minimized. In this mapping, some delay factors,
such as the message sending probability of cores, the packet length, and the
network contention for communication, are not been considered. Zhou et al.
(2006) proposed a delay model for application mapping onto NoC considering
all these factors. Their proposed GA-based delay model can map the application onto NoC optimally with a minimum average delay. PLBMR, a PSO-based
two-phase application mapping algorithm proposed by Zhou et al. (2007),
minimizes the NoC communication energy and allocates the routing path for
balancing the link load. In the first phase, the PSO maps IP cores onto NoC
to minimize the energy consumption, and in the second phase, the routing
paths are allocated to every pair to satisfy the link–load balance. Ascia et al.
(2004) proposed a pareto-based multiobjective evolutionary computing technique that optimizes the performance and power consumption of mapped
NoC. Ascia et al. (2006) used the above technique for application task mapping. For dynamic evaluation, an event-driven trace-based simulator was used
to compare their results with a pareto-based branch-and-bound approach and
a pareto-based NMAP approach. A multiobjective GA-based application mapping for NoC was presented by Benyamina and Boulet (2007), which targets
mapping with a network assignment (NA) for heterogeneous distributed
embedded systems to improve the performance and reduce the power consumption and area. This technique first allocates tasks to cores and then maps
the cores to different tiles of NoC satisfying communication requirements.
The mapping of IP cores onto NoC tiles, together with routing path allocation, is referred to as NA. The NA is usually performed after task mapping to
reduce the on-chip intercommunication distance. The GA-based optimization
technique, MGAP, proposed by Jena and Sharma (2007) minimizes the power
consumption by reducing the number of switches in the communication path
between cores and also maximizes the throughput. Although Lei and Kumar
(2003) used a similar technique, they considered the dynamic effect of traffic.
They also gave a set of solutions using pareto mapping as used in the work of
Ascia et al. (2004, 2006). A multiobjective GA (MOGA)-based application mapping technique was proposed by Bhardwaj and Jena (2009), where one–one
as well as many–many mapping between switches and tiles were taken into
consideration to minimize energy consumption and the required link bandwidth. It is used to find an optimal solution from the pareto optimal solutions
as in the work of Jena and Sharma (2007). Darbari et al. (2009a, 2009b) proposed
CGMAP, a GA-based application mapping technique that uses the chaotic
mapping operator instead of the random processes in GA. Fard et al. (2009)