Preface
xv
• Chapter 9 discusses the problem of synthesizing application-specific
NoCs. The NoC synthesis problem addresses the issue of evolving
the best possible NoC topology for a given application task graph. It
includes the issues such as topology generation, router placement,
and scheduling algorithm development on the designed topology.
• Chapter 10 deals with reconfigurable NoC design issues. The subtopics include using field programmable gate array (FPGA) for NoC
reconfiguration, designing a router architecture that aids in dynamic
change of interconnection pattern between the routers, reconfigurable link design, and revisiting the application mapping problem
from the reconfiguration viewpoint.
• Chapter 11 highlights the limited floorplanning choices of 2D NoC
and also focuses on 3D NoC design, which is the amalgamation of
2D NoC and 3D IC. In 3D IC, multiple layers of active silicon are
stacked using special vertical interconnects, known as through-silicon
via. The actual benefit of 3D IC relies on the fact that the relatively
long wires (approximately in millimeters) of 2D IC can be replaced
by these TSVs whose lengths are about tens of microns. This chapter
explores the design space of integrating multiple cores onto different
silicon layers focusing on the performance and cost metrics.
• Finally, Chapter 12 presents the conclusions and enumerates the
directions for future research and development in the field of NoC.
Santanu Kundu
LSI India Research and Development Pvt. Ltd.
(An Avago Technologies Company)
Santanu Chattopadhyay
Indian Institute of Technology, Kharagpur
xv
• Chapter 9 discusses the problem of synthesizing application-specific
NoCs. The NoC synthesis problem addresses the issue of evolving
the best possible NoC topology for a given application task graph. It
includes the issues such as topology generation, router placement,
and scheduling algorithm development on the designed topology.
• Chapter 10 deals with reconfigurable NoC design issues. The subtopics include using field programmable gate array (FPGA) for NoC
reconfiguration, designing a router architecture that aids in dynamic
change of interconnection pattern between the routers, reconfigurable link design, and revisiting the application mapping problem
from the reconfiguration viewpoint.
• Chapter 11 highlights the limited floorplanning choices of 2D NoC
and also focuses on 3D NoC design, which is the amalgamation of
2D NoC and 3D IC. In 3D IC, multiple layers of active silicon are
stacked using special vertical interconnects, known as through-silicon
via. The actual benefit of 3D IC relies on the fact that the relatively
long wires (approximately in millimeters) of 2D IC can be replaced
by these TSVs whose lengths are about tens of microns. This chapter
explores the design space of integrating multiple cores onto different
silicon layers focusing on the performance and cost metrics.
• Finally, Chapter 12 presents the conclusions and enumerates the
directions for future research and development in the field of NoC.
Santanu Kundu
LSI India Research and Development Pvt. Ltd.
(An Avago Technologies Company)
Santanu Chattopadhyay
Indian Institute of Technology, Kharagpur