Application
Network
interface
Traffic modeling
BMAP
Mapping
Hardware cost
optimization
Performance
evaluation
Final
NoC
Figure 5.3
OCN design flow in BMAP.
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Application Mapping on Network-on-Chip
known as binomial mapping (BMAP) algorithm (Shen et al. 2007). It works in
the context of mesh topology. The on-chip network (OCN) design flow in
BMAP is shown in Figure 5.3. Given a system-on-chip (SoC) application to
be implemented, first the designer chooses the NI to be used by the cores.
It is assumed that the target NoC will utilize the wormhole architecture
for the routers, and thus, every packet consists of a header flit, a number
of body flits, and a tail flit. From the given SoC application, a traffic model
is extracted. The OCN synthesis process in BMAP can be divided into the
following three stages:
• Mapping: It performs a mapping of the application task graph onto
the topology graph.
• Optimization: The mapped network is optimized at this stage.
• Simulation: A cycle-accurate simulator can be used to evaluate the
performance of the synthesized NoC.
Out of these three stages, the mapping and the optimization phases constitute the BMAP algorithm.