Preface
System-on-chip (SoC) is a paradigm for designing today’s integrated circuit
(IC) chips that put an entire system onto a single silicon floor (instead of
printed circuit boards containing a number of chips accomplishing the system task). With the increasing number of cores integrated on such a chip,
on-chip communication efficiency has become one of the key factors in
determining the overall system performance and cost. The communication
medium used in most of the modern SoCs is a shared global bus. In spite of
its fairly simple structure, extensibility, and low area cost, at the system level,
it can be used for only up to tens of cores on a single chip. This restriction is
mainly due to the following reasons: nonscalable wire delay with technology
shrinking, nonscalable system performance with number of cores attached,
decrease in operating frequency with each additional core attached, high
power consumption in long wires, and so on. In many-core-based SoCs, the
major challenge that designers face today is to come up with a scalable, reusable, and high-performance communication backbone.
Network-on-chip (NoC) is an emerging alternative that overcomes the
above-mentioned bottlenecks for integrating a large number of cores on a
single SoC. NoC is a specific flavor of interconnection networks where the
cores communicate with each other using a router-based packet-switched
network. Interconnection networks have been studied for more than the past
two decades and a solid foundation of design techniques has been reported
in the literature. NoC is today becoming an emerging research and development topic including hardware communication infrastructure design, software and operating system services, computer aided design (CAD) tools for
NoC synthesis, NoC testing, and so on.
However, two-dimensional (2D) IC design has limited floorplanning
choices with increasing number of cores attached. An attractive solution to
this problem is the three-dimensional (3D) IC technology that stacks multiple layers of active silicon using special vertical interconnects, known as
through-silicon via (TSV). The introduction of 2D NoC in a 3D IC platform is
a gradual process and is known as 3D NoC. Although a number of 2D NoC
implementations have already been fabricated in industries (e.g., Intel, IBM,
Arteris, Tilera, etc.), research in 3D NoC is still in its infancy and demands
more concentration from academia and industries.
Aim and scope: This book aims to cover the important aspects of NoC
design: communication infrastructure design, communication methodology,
evaluation framework, mapping of applications onto NoC, and so on. Apart
from these, it also proposes to focus on other upcoming NoC issues, such
as low-power NoC design, signal integrity issues, NoC testing, synthesis,
reconfiguration, and 3D NoC design.
xiii
System-on-chip (SoC) is a paradigm for designing today’s integrated circuit
(IC) chips that put an entire system onto a single silicon floor (instead of
printed circuit boards containing a number of chips accomplishing the system task). With the increasing number of cores integrated on such a chip,
on-chip communication efficiency has become one of the key factors in
determining the overall system performance and cost. The communication
medium used in most of the modern SoCs is a shared global bus. In spite of
its fairly simple structure, extensibility, and low area cost, at the system level,
it can be used for only up to tens of cores on a single chip. This restriction is
mainly due to the following reasons: nonscalable wire delay with technology
shrinking, nonscalable system performance with number of cores attached,
decrease in operating frequency with each additional core attached, high
power consumption in long wires, and so on. In many-core-based SoCs, the
major challenge that designers face today is to come up with a scalable, reusable, and high-performance communication backbone.
Network-on-chip (NoC) is an emerging alternative that overcomes the
above-mentioned bottlenecks for integrating a large number of cores on a
single SoC. NoC is a specific flavor of interconnection networks where the
cores communicate with each other using a router-based packet-switched
network. Interconnection networks have been studied for more than the past
two decades and a solid foundation of design techniques has been reported
in the literature. NoC is today becoming an emerging research and development topic including hardware communication infrastructure design, software and operating system services, computer aided design (CAD) tools for
NoC synthesis, NoC testing, and so on.
However, two-dimensional (2D) IC design has limited floorplanning
choices with increasing number of cores attached. An attractive solution to
this problem is the three-dimensional (3D) IC technology that stacks multiple layers of active silicon using special vertical interconnects, known as
through-silicon via (TSV). The introduction of 2D NoC in a 3D IC platform is
a gradual process and is known as 3D NoC. Although a number of 2D NoC
implementations have already been fabricated in industries (e.g., Intel, IBM,
Arteris, Tilera, etc.), research in 3D NoC is still in its infancy and demands
more concentration from academia and industries.
Aim and scope: This book aims to cover the important aspects of NoC
design: communication infrastructure design, communication methodology,
evaluation framework, mapping of applications onto NoC, and so on. Apart
from these, it also proposes to focus on other upcoming NoC issues, such
as low-power NoC design, signal integrity issues, NoC testing, synthesis,
reconfiguration, and 3D NoC design.
xiii